ZL50120 Zarlink, ZL50120 Datasheet - Page 92

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

16.0
API
ATM
CDP
CESoP
CESoPSN Circuit Emulation Services over Packet Switched Networks
CONTEXT A programmed connection of a number of TDM timeslots assembled into a unique packet stream.
CPU
DMA
DPLL
DSP
GMII
H.100/H.110High capacity TDM backplane standards
H-MVIP
IETF
IA
IP
JTAG
L2TP
LAN
LIU
MAC
MEF
MFA
MII
MIB
MPLS
MTIE
MVIP
PDH
PLL
PRS
PRX
PSTN
Glossary
Application Program Interface
Asynchronous Transfer Mode
Context Descriptor Protocol (the protocol used by Zarlink’s MT9088x family of TDM-Packet devices)
Circuit Emulation Services over Packet
Central Processing Unit
Direct Memory Access
Digital Phase Locked Loop
Digital Signal Processor
Gigabit Media Independent Interface
High-performance Multi-Vendor Integration Protocol (a TDM bus standard)
Internet Engineering Task Force
Implementation Agreement
Internet Protocol (version 4, RFC 791, version 6, RFC 2460)
Joint Test Algorithms Group (generally used to refer to a standard way of providing a board-level test
facility)
Layer 2 Tunneling Protocol (RFC 2661)
Local Area Network
Line Interface Unit
Media Access Control
Metro Ethernet Forum
MPLS and Frame Relay Alliance
Media Independent Interface
Management Information Base
Multi Protocol Label Switching
Maximum Time Interval Error
Multi-Vendor Integration Protocol (a TDM bus standard)
Plesiochronous Digital Hierarchy
Phase Locked Loop
Primary Reference Source
Packet Receive
Public Switched Telephone Circuit
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
92
Data Sheet