ZL50120 Zarlink, ZL50120 Datasheet - Page 83

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of
CPU_TA, not at the positive clock edge during the assertion of CPU_TA.
CPU_ADDR[23:2]
CPU_DATA[31:0]
CPU_ADDR[23:2]
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TS_ALE
CPU_CLK
CPU_WE
CPU_CS
CPU_OE
CPU_TA
CPU_CLK
CPU_WE
CPU_CS
CPU_OE
CPU_TA
NOTE: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS
and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted.
CPU_CS and CPU_OE must BOTH be asserted to enable the CPU_DATA output.
NOTE: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS
until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is
finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed.
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ZL50115/16/17/18/19/20
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Figure 41 - CPU Write - MPC8260
CAH
CTH
Figure 40 - CPU Read - MPC8260
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Zarlink Semiconductor Inc.
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