ZL50120 Zarlink, ZL50120 Datasheet - Page 71

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

12.2
These parameters are based on the H.110 Specification from the Enterprise Computer Telephony Forum (ECTF)
1997.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
TDM_C8 Period
TDM_C8 High
TDM_C8 Low
TDM_D Output Delay
TDM_D Output to HiZ
TDM_D HiZ to Output
TDM_D Input Delay to Valid
TDM_D Input Delay to Invalid
TDM_FRAME width
TDM_FRAME setup
TDM_FRAME hold
Phase Correction
TDM Interface Timing - H.110 Mode
TDM_C8 and TDM_FRAME signals are required to meet the same timing standards and so are not defined independently.
TDM_C8 corresponds to pin TDM_CLKi.
t
Refer to H.110 Standard from Enterprise Computer Telephony Forum (ECTF) for the source of these numbers.
The TDM_FRAME signal is centred on the rising edge of TDM_C8. All timing measurements are based on this rising edge
Phase correction ( Φ ) results from DPLL timing corrections.
point; TDM_FRAME corresponds to pin TDM_F0i.
DOZ
TDM_CLKO (2.048 MHz)
TDM_CLKO (4.096 MHz)
Parameter
and t
ZDO
apply at every time-slot boundary.
TDM_STo
TDM_F0o
TDM_STi
Figure 28 - TDM Bus Master Mode Timing at 2.048 Mbps
Table 26 - TDM H.110 Timing Specification
Channel 31 Bit 0
Symbol
t
t
t
t
t
Ch 31 Bit 0
t
t
DOD
DOZ
ZDO
t
t
C8P
C8H
t
t
C8L
DIV
DV
FP
FS
FH
F
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
122.066-Φ
t
FOD
63-Φ
63-Φ
Min.
102
90
45
45
0
0
0
0
-
t
71
STOD
t
C4OP
Channel 0 Bit 7
t
FOD
Typ.
122
122
Ch 0 Bit 7
t
-
-
-
-
-
-
-
-
-
-
C2OP
t
t
STIH
STIS
122.074+Φ
69+Φ
69+Φ
Max.
112
180
33
83
90
90
10
11
11
t
STOD
Channel 0 Bit 6
Units
Ch 0 Bit 6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 2
Load - 12 pF
Load - 12 pF
Note 3
Load - 12 pF
Note 3
Note 4
Note 4
Note 5
Note 6
Data Sheet
Notes