ZL50120 Zarlink, ZL50120 Datasheet - Page 60

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

9.0
The ZL5011x family incorporates an internal DPLL that meets Telcordia GR-1244-CORE Stratum 3 and Stratum
4/4E requirements, assuming an appropriate clock oscillator is connected to the system clock pin. It will meet the
jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase
change slope, holdover frequency and MTIE requirements for these specifications. In structured mode with the
ZL5011x device operating as a master the DPLL is used to provide clock and frame reference signals to the internal
and external TDM infrastructure. In structured mode, with the ZL5011x device operating as a slave, the DPLL is not
used. All TDM clock generation is performed externally and the input streams are synchronised to the system clock
by the TDM interface. The DPLL is not required in unstructured mode, where TDM clock and frame signals are
generated by internal DCO’s assigned to each individual stream.
9.1
It can be set into one of four operating modes: Locking mode, Holdover mode, Freerun mode and Powerdown
mode.
9.1.1
The DPLL accepts a reference signal from either a primary or secondary source, providing redundancy in the event
of a failure. These references should have the same nominal frequencies but do not need to be identical as long as
their frequency offsets meet the appropriate Stratum requirements. Each source is selected from any one of the
available TDM input stream clocks (up to 4 on the ZL50117/20 variants), or from the external TDM_CLKiP (primary)
or TDM_CLKiS (secondary) input pins, as illustrated in Figure 16 - on page 51. It is possible to supply a range of
input frequencies as the DPLL reference source, depicted in Table 24. The PRD register Value is the number (in
hexadecimal) that must be programmed into the PRD register within the DPLL to obtain the divided down frequency
at PLL_PRI or PLL_SEC.
Note 1:
Note 2:
Note 3:
Input Frequency
44.736 (Note 3)
Modes of Operation
DPLL Specification
Source
16.384
22.368
34.368
A PRD/SRD value of 0 will suppress the clock, and prevent it from reaching the DPLL.
UI means Unit Interval - in this case periods of the time signal. So ±1UI on a 64 kHz signal means ±15.625 µs, the period of
This input frequency is supported with the use of an external divide by 2.
(MHz)
the reference frequency. Similarly ±1023UI on a 4.096 MHz signal means ±250 µs.
0.008
1.544
2.048
4.096
8.192
6.312
Locking Mode (normal operation)
Tolerance
(±ppm)
130
30
50
50
50
50
30
20
20
20
Table 24 - DPLL Input Reference Frequencies
ZL50115/16/17/18/19/20
Divider
Ratio
2796
537
699
1
1
1
1
1
1
1
Zarlink Semiconductor Inc.
60
PRD/SRD
Register
(Note 1)
Value
(Hex)
AEC
2BB
219
1
1
1
1
1
1
1
Frequency at
PLL_PRI or
PLL_SEC
16.384
(MHz)
0.008
1.544
2.048
4.096
8.192
6.312
0.008
0.064
0.064
±1 (on 64k Hz)
±1 (on 64 kHz)
±1 (on 64 kHz)
Input Wander
Acceptable
Maximum
tolerance
(Note 2)
Data Sheet
±1023
±1023
±1023
±1023
±1023
±1023
(UI)
±1