ZL50120 Zarlink, ZL50120 Datasheet - Page 89

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

In Summary:
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14.1.1
The GMII interface passes data to and from the ZL5011x with their related transmit and receive clocks. It is
therefore recommended that the trace lengths for transmit related signals and their clock and the receive related
signals and their clock are kept to the same length. By doing this the skew between individual signals and their
related clock will be minimized.
14.1.2
Although the data rate of this interface is low the outputs edge speeds share the characteristics of the higher data
rate outputs and therefore must be treated with the same care extended to the other interfaces with particular
reference to the lower stream numbers which support the higher data rates. The TDM interface has numerous
clocking schemes and as a result of this the input clock traces to the ZL5011x devices should be treated with care.
14.1.3
Particular effort should be made to minimize crosstalk from ZL5011x outputs and ensuring fast rise time to these
inputs.
In Summary:
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Place series termination resistors as close to the pins as possible
minimize output capacitance
Keep common interface traces close to the same length to avoid skew
Protect input clocks and signals from crosstalk
Place series termination resistors as close to the pins as possible
minimize output capacitance
Keep common interface traces close to the same length to avoid skew
Protect input clocks and signals from crosstalk
GMAC Interface - Special Considerations During Layout
TDM Interface - Special Considerations During Layout
Summary
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
89
Data Sheet