ZL50120 Zarlink, ZL50120 Datasheet - Page 33

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

M0_CRS /
M0_Signal_Detect
M0_TXCLK
M0_TXD[7:0]
M0_TXEN /
M0_TXD[8]
M0_TXER /
M0_TXD[9]
M0_GTX_CLK
Signal
Table 8 - MII Port 0 Interface Package Ball Definition (continued)
I/O
I D
I U
O
O
O
O
B6
A3
[7]
[6]
[5]
[4]
A9
B10
A8
C11
D12
B12
C12
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
[3]
[2]
[1]
[0]
MII Port 0
33
B13
B14
D13
C13
GMII/MII - M0_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active high.
TBI - M0_Signal Detect
Similar function to M0_CRS.
MII only - Transmit Clock
Accepts the following frequencies:
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_TXCLK (MII) or the rising edge
of M0_GTXCLK (GMII/TBI).
GMII/MII - M0_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M0_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
TBI - M0_TXD[8]
Transmit Data. Clocked on rising edge of
M0_GTXCLK.
GMII/MII - M0_TXER
Transmit Error. Transmitted synchronously
with respect to M0_TXCLK, and active high.
When asserted (with M0_TXEN also
asserted) the ZL5011x will transmit a
non-valid symbol, somewhere in the
transmitted frame.
TBI - M0_TXD[9]
Transmit Data. Clocked on rising edge of
M0_GTXCLK.
GMII/TBI only - Gigabit Transmit Clock
Output of a clock for Gigabit operation at
125 MHz.
25.0 MHz
MII
Description
100 Mbps
Data Sheet