ZL50120 Zarlink, ZL50120 Datasheet - Page 59

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

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8.9
8.9.1
The ZL5011x family supports the following modes of operation.
8.9.1.1
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this
mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access
Port and Boundary Scan Architecture.
Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
8.9.1.2
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the
development board.
8.9.2
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 23.
8.9.3
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default
mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of
the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins
may be configured by the ADM module as either inputs or outputs.
8.9.4
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
SYS_NORMAL_MODE
SYS_TRI_STATE_MODE
System clock speed of 100 MHz
Host clock speed of up to 66 MHz
Debug option to freeze all internal state machines
JTAG (IEEE1149) Test Access Port
3.3 V I/O Supply rail with 5 V tolerance
1.8 V Core Supply rail
Fully compatible with MT90880/1/2/3 and ZL50110/11/14 Zarlink product line
System Test Mode
Miscellaneous Features
Test Modes Operation
Overview
Test Mode Control
System Normal Mode
System Tri-state Mode
Table 23 - Test Mode Control
System Normal Mode
System Tri-State Mode
test_mode[2:0]
3’b000
3’b011
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
59
Data Sheet