ZL50120 Zarlink, ZL50120 Datasheet - Page 28

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

4.1.2
TDM_CLKi_REF
TDM_CLKo_REF
TDM_FRMi_REF
TDM_FRMo_REF
AUX_CLKI
AUX_CLKO
Signal
TDM Signals common to ZL50115/16/17/18/19/20
I/O
OT
I D
I D
I D
O
O
W2
V3
T3
W3
L3
L2
Table 4 - TDM Interface Common Pin Definition
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
28
TDM port reference clock input for
backplane operation
TDM port reference clock output for
backplane operation
TDM port reference frame input. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0i
H.110:
H-MVIP:
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
TDM port reference frame output. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0o
H.110:
H-MVIP:
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
Auxiliary clock input. Typically connected to
AUX_CLKO.
Auxiliary clock output. Typically connected
to AUX_CLKI.
TDM_FRAME
TDM_FRAME
TDM_F0
TDM_F0
Description
Data Sheet