ZL50120 Zarlink, ZL50120 Datasheet - Page 38

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

4.5
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock.
4.6
4.6.1
All Administration, Control and Test Interface signals are 5 V tolerant.
SYSTEM_CLK
SYSTEM_RST
SYSTEM_DEBUG
GPIO[15:0]
TEST_MODE[2:0]
System Function Interface
Test Facilities
Signal
Administration, Control and Test Interface
Signal
Table 12 - Administration/Control Interface Package Ball Definition
Table 11 - System Function Interface Package Ball Definition
I/O
OT
ID/
I D
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[2]
[1]
[0]
I/O
I
I
I
W13
AA12
AA11
W17
Y16
AB16
AA16
AB15
AB14
W15
Y15
AB17
Y17
AA17
ZL50115/16/17/18/19/20
Package Balls
Package Balls
Zarlink Semiconductor Inc.
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
38
AA15
AB13
AB12
AB11
AB10
AA14
AA13
AB9
General Purpose I/O pins. Connected to an
internal register, so customer can set
user-defined parameters. Bits [4:0] reserved
at start-up or reset for memory TDL setup.
See the ZL50115/16/17/18/19/20
Programmers Model for more details.
Recommend 5 kohm pulldown on these
signals.
Test Mode input - ensure these pins are tied
to ground for normal operation.
000 SYS_NORMAL_MODE
001-010 RESERVED
011 SYS_TRISTATE_MODE
100-111 RESERVED
System Clock Input. The system clock
frequency is 100 MHz. The frequency
must be accurate to within ±32 ppm in
synchronous mode.
System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the /1/4 to be
reset to their default state.
System Debug Enable.
asynchronous
de-asserted,
assertion of the debug-freeze command,
regardless of the internal state of
registers, or any error conditions. Active
high.
Description
Description
prevents
signal
the
that,
Data Sheet
This is an
software
when