ZL50120 Zarlink, ZL50120 Datasheet - Page 56

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

7.2
For applications where there is no common reference clock between provider edge units, an adaptive clock
recovery technique is provided. This infers the clock rate of the original TDM service clock from the mean arrival
rate of packets at the packet egress point.
The disadvantage of this type of scheme is that, depending on the characteristics of the packet network, it may
prove difficult to regenerate a clock that stays within the wander requirements of the plesiochronous digital
hierarchy (specifically MTIE). The reason for this is that any variation in delay between packets will feed through as
a variation in the frequency of the recovered clock. High frequency jitter can be filtered out, but any low frequency
variation or wander is more difficult to remove without a very long time constant. This will in turn affect the ability of
the system to lock to the original clock within an acceptable time.
With no PRS clock the only information available to determine the TDM transmission speed is the average arrival
rate of the packets, as shown in Figure 21. Timestamps representing the number of elapsed source clock periods
may be included in the packet header, or information can be inferred from a known payload size at the destination.
It is possible to maintain average buffer-fill levels at the destination, where an increase or decrease in the fill level of
the buffer would require a change in transmission clock speed to maintain the average. Additionally, the buffer-fill
depth can be altered independently, with no relation to the recovered clock frequency, to control TDM transmission
latency.
8.0
8.1
The following lists the intrinsic processing latency of the ZL5011x. The intrinsic processing latency is dependent on
the number of channels in a context for structured operation, as detailed below. However, the intrinsic processing
latency is not dependent on the total number of contexts opened or the total number of channels being processed
by the device.
•
•
•
•
TDM to Packet transmission processing latency less than 125 µs
Packet to TDM transmission processing latency less than 250 µs (unstructured)
Packet to TDM transmission processing latency less than 250 µs (structured, more than 16 channels in
context)
Packet to TDM transmission processing latency less than 375 µs (structured, 16 or less channels in context)
Adaptive Clock Recovery
Latency
System Features
LIU
Data
Source
Clock
ZL5011x
source
node
Figure 21 - Adaptive Clock Recovery
ZL50115/16/17/18/19/20
Packets
Zarlink Semiconductor Inc.
Network
56
Packets
ZL5011x
destination
node
Host CPU
monitor
Queue
DCO
Data
Dest'n
Clock
LIU
Data Sheet