ZL50120 Zarlink, ZL50120 Datasheet - Page 86

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

12.9
Note 1:
Note 2:
Note 3:
JTAG_CLK period
JTAG_CLK clock pulse width
JTAG_CLK rise and fall time
JTAG_TRST setup time
JTAG_TRST assert time
Input data setup time
Input Data hold time
JTAG_CLK to Output data valid
JTAG_CLK to Output data high
impedance
JTAG_TMS, JTAG_TDI setup time
JTAG_TMS, JTAG_TDI hold time
JTAG_TDO delay
JTAG_TDO delay to high
impedance
JTAG Interface Timing
JTAG_TRST is an asynchronous signal. The setup time is for test purposes only.
Non Test (other than JTAG_TDI and JTAG_TMS) signal input timing with respect to JTAG_CLK.
Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK.
JTAG_TMS
JTAG_TDO
JTAG_TCK
JTAG_TDI
Parameter
t
TPSU
t
HIGH
t
TPH
Don't Care
HiZ
Symbol
Table 38 - JTAG Interface Timing
t
t
ZL50115/16/17/18/19/20
RSTSU
t
TOPDV
t
t
t
t
t
t
TPSU
t
t
LOW,
HIGH
t
RST
TPH
JCP
JRF
JSU
t
JDV
t
TPZ
JH
Figure 44 - JTAG Signal Timing
JZ
t
LOW
Zarlink Semiconductor Inc.
Min.
40
20
10
10
15
15
0
5
0
0
5
0
0
86
t
TOPDV
Typ.
t
100
TPSU
-
-
-
-
-
-
-
-
-
-
-
-
t
JCP
Max.
20
20
15
15
3
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
TPZ
t
TPH
With respect to
JTAG_CLK
falling edge.
Note 1
Note 2
Note 2
Note 3
Note 3
HiZ
DC
Data Sheet
Notes