ZL50120 Zarlink, ZL50120 Datasheet - Page 85

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

12.8
Note 1:
Note 2:
Note 3:
Note 4:
SYSTEM_CLK Frequency
SYSTEM_CLK accuracy
(synchronous master mode)
SYSTEM_CLK accuracy
(synchronous slave mode and
asynchronous mode)
System Function Port
The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a
The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and
The absolute SYSTEM_CLK accuracy must be controlled to ± 30 ppm in synchronous master mode to enable the internal
In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may
short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover
Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the
system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature
coefficient of 0.1 ppm/ºC, a 10ºC change in temperature while the DPLL is in will result in a frequency accuracy offset of
1 ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift.
synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e., frequency of clock output
equals 8.192 MHz ± SYSTEM_CLK accuracy ± 0.005 ppm).
DPLL to function correctly.
be relaxed slightly.
Parameter
Symbol
CLK
CLK
CLK
Table 37 - System Clock Timing
ZL50115/16/17/18/19/20
ACS
ACA
FR
Zarlink Semiconductor Inc.
Min.
-
-
-
85
Typ.
100
-
-
Max.
±200
±30
-
Units
MHz
ppm
ppm
Note 1 and Note
2
Note 3
Note 4
Data Sheet
Notes