ZL50120 Zarlink, ZL50120 Datasheet - Page 75

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

12.5
12.6
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
12.6.1
TDM_CLKiP High / Low
Pulsewidth
TDM_CLKiS High / Low
Pulsewidth
TXCLK period
TXCLK high time
TXCLK low time
TXCLK rise time
TXCLK fall time
TXCLK rise to TXD[3:0] active
delay (TXCLK rising edge)
TXCLK to TXEN active delay
(TXCLK rising edge)
TXCLK to TXER active delay
(TXCLK rising edge)
PAC Interface Timing
Packet Interface Timing
MII Transmit Timing
Parameter
Parameter
Table 30 - MII Transmit Timing - 100 Mbps
Symbol
Table 29 - PAC Timing Specification
t
t
t
CLO
t
t
t
t
t
CHI
CC
CR
Symbol
CF
DV
EV
ER
ZL50115/16/17/18/19/20
t
t
CPP
CSP
Zarlink Semiconductor Inc.
Min.
14
14
1
1
1
Min.
-
-
-
10
10
75
100 Mbps
Typ.
Typ.
40
-
-
-
-
-
-
-
-
-
Max.
-
-
Max.
26
26
25
25
25
5
5
-
Units
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
Load = 25 pF
Load = 25 pF
Load = 25 pF
Data Sheet
Notes
Notes