ZL50120 Zarlink, ZL50120 Datasheet - Page 76

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

12.6.2
RXCLK period
RXCLK high wide time
RXCLK low wide time
RXCLK rise time
RXCLK fall time
RXD[3:0] setup time (RXCLK
rising edge)
RXD[3:0] hold time (RXCLK
rising edge)
RXDV input setup time
(RXCLK rising edge)
RXDV input hold time (RXCLK
rising edge)
RXER input setup time (RXCL
edge)
RXER input hold time (RXCLK
rising edge)
TXD[3:0]
MII Receive Timing
TXCLK
Parameter
TXEN
TXER
t
t
EV
DV
Table 31 - MII Receive Timing - 100 Mbps
Symbol
Figure 32 - MII Transmit Timing Diagram
t
t
t
t
t
t
t
t
t
DVH
ERH
t
t
DVS
ERS
CC
CH
CR
CF
DS
DH
CL
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
t
ER
Min.
14
14
10
10
10
5
5
5
-
-
-
t
CC
76
100 Mbps
Typ.
40
20
20
-
-
-
-
-
-
-
-
t
ER
t
CL
Max.
26
26
5
5
-
-
-
-
-
-
-
t
CH
t
EV
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
Notes