ZL50120 Zarlink, ZL50120 Datasheet - Page 30

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

4.3
For the ZL50118/19/20 variants the packet interface is capable of either 2 MII interfaces, or 1 MII and 1 GMII
interfaces, or 1 MII and 1 TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an
integrated 1000BASE-X PCS module. The ZL50118/19/20 supports Port 0 and Port 1.
For the ZL50115/16/17 variants the packet interface is capable of 1 MII or 1 GMII or 1 TBI (1000 Mbps) interface.
The TBI interface is a PCS interface supported by an integrated 1000BASE-X PCS module. The ZL50115/16/17
supports Port 0.
Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. Only Port 0 has the
1000 Mbps capability necessary for the GMII/TBI interface.
Table 6 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 7 shows all
the pins and their related package ball, but is based on the GMII/MII configuration.
All Packet Interface signals are 5V tolerant, and all outputs are high impedance while System Reset is LOW.
Note: Mn can be either M0 or M1 for ZL5011x variants.
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_RXD[3:0]
Mn_TXD[3:0]
Packet Interfaces
Table 6 - Packet Interface Signal Mapping - MII to GMII/TBI
Mn_RXCLK
Mn_TXCLK
Mn_RXDV
Mn_RXER
Mn_TXEN
Mn_TXER
Mn_CRS
Mn_COL
MII
-
-
-
Mn_GIGABIT_LED
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_GTX_CLK
Mn_RXD[7:0]
Mn_REFCLK
Mn_TXD[7:0]
Mn_RXCLK
Mn_RXDV
Mn_RXER
Mn_TXEN
Mn_TXER
Mn_COL
Mn_CRS
GMII
-
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
Mn_GIGABIT_LED
Mn_Signal_Detect
Mn_LINKUP_LED
Mn_ACTIVE_LED
30
Mn_GTX_CLK
Mn_RXD[7:0]
Mn_REFCLK
Mn_TXD[7:0]
Mn_RXD[8]
Mn_RXD[9]
Mn_TXD[8]
Mn_TXD[9]
TBI (PCS)
Mn_RBC0
Mn_RBC1
-
Data Sheet