ZL50120 Zarlink, ZL50120 Datasheet - Page 62

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the
event of an invalid signal regardless of mode.
9.3
When the reference source the DPLL is currently locking to becomes invalid, the DPLL’s response depends on
which one of the failure detect modes has been chosen: autodetect, forced primary, or forced secondary. One of
these failure detect modes must be chosen via the FDM1:0 bits of the DOM register. After a device reset via the
SYSTEM_RESET pin, the autodetect mode is selected.
In autodetect mode (automatic reference switching) if both references are valid the DPLL will synchronise to the
preferred reference. If the preferred reference becomes unreliable, the DPLL continues driving its output clock in a
stable holdover state until it makes a switch to the backup reference. If the preferred reference recovers, the DPLL
makes a switch back to the preferred reference. If necessary, the switch back can be prevented by changing the
preferred reference using the REFSEL bit in the DOM register, after the switch to the backup reference has
occurred.
If both references are unreliable, the DPLL will drive its output clock using the stable holdover values until one of
the references becomes valid.
In forced primary mode, the DPLL will synchronise to the primary reference only. The DPLL will not switch to the
secondary reference under any circumstances including the loss of the primary reference. In this condition, the
DPLL remains in holdover mode until the primary reference recovers. Similarly in forced secondary mode, the
DPLL will synchronise to the secondary reference only, and will not switch to the primary reference. Again, a failure
of the secondary reference will cause the DPLL to enter holdover mode, until such time as the secondary reference
recovers. The choice of preferred reference has no effect in these modes.
When a conventional PLL is locked to its reference, there is no phase difference between the input reference and
the PLL output. For the DPLL, the input references can have any phase relationship between them. During a
reference switch, if the DPLL output follows the phase of the new reference, a large phase jump could occur. The
phase jump would be transferred to the TDM outputs. The DPLL’s MTIE (Maximum Time Interval Error) feature
preserves the continuity of the DPLL output so that it appears no reference switch had occurred. The MTIE circuit is
not perfect however, and a small Time Interval Error is still incurred per reference switch. To align the DPLL output
clock to the nearest edge of the selected input reference, the MTIE reset bit (MRST bit in the DOM register) can be
used.
Unlike some designs, switching between references which are at different nominal frequencies do not require
intervention such as a system reset.
9.4
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to
maintain the synchronization. The locking range is programmable up to ±372 ppm.
Note that the locking range relates to the system clock frequency. If the external oscillator has a tolerance of
-100 ppm, and the locking range is programmed to ±200 ppm, the actual locking range is the programmed value
shifted by the system clock tolerance to become -300 ppm to +100 ppm.
9.5
The Locking Time is the time it takes the synchroniser to phase lock to the input signal. Phase lock occurs when the
input and output signals are not changing in phase with respect to each other (not including jitter).
Locking time is very difficult to determine because it is affected by many factors including:
•
•
initial input to output phase difference
initial input to output frequency difference
Locking Mode Reference Switching
Locking Range
Locking Time
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
62
Data Sheet