ZL50120 Zarlink, ZL50120 Datasheet - Page 57

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The
transmit latency is the sum of the transmit processing and the number of frames per packet x 125 µs. The receive
latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to
compensate for packet network PDV.
The ZL5011x is capable of creating an extremely low latency connection, with end to end delays of less than
0.5 ms, depending on user configuration.
8.2
The ZL5011x devices support loopback of the TDM circuits and the circuit emulation packets.
TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload
Assembly blocks. The packetized data is then routed by the Task Manager back to the same TDM port via the TDM
Formatter and TDM Interface.
Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks,
back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new
header directing the packets back to the source.
8.3
The control processor can generate packets directly, allowing it to use the network for out-of-band communications.
This can be used for transmission of control data or network setup information, e.g., routing information. The host
interface can also be used by a local resource for network transmission of processed data.
The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own
DMA controller. Table 22 illustrates the maximum bandwidths achievable by an external DMA master.
Note 1:
Note 2:
8.4
During normal transmission a situation may arise where a Loss of Service occurs, caused by a disruption in the
transmission line due to engineering works or cable disconnection for example. This results in the loss of a TDM
signal, including the associated TDM clock, from the LIU.
With no TDM signal or clock, no packets can be assembled by the transmitting ZL5011x device, and the flow of
packets will cease. The absence of packets at the receiving ZL5011x device will cause underrun data to be
generated at the TDM output, normally an “all-ones” pattern, with the exception of DS3 which alternates ones and
zeros. The LOS condition is detected by the receive ZL5011x device.
Additionally, when the LIU detects LOS, it can notify the CPU. The CPU can set a control bit in the packet header
(bit L in the IETF drafts), which is then transmitted. The receiving ZL5011x device recognizes the control bit, and
transmits an AIS (all-ones) pattern on the appropriate TDM stream.
ZL5011x to CPU only
ZL5011x to CPU only
CPU to ZL5011x only
CPU to ZL5011x only
Loopback Modes
Host Packet Generation
Loss of Service (LOS)
Maximum bandwidths are the maximum the ZL5011x devices can transfer under host control, and assumes only minimal
Combined figures assume the same amount of data is to be transferred each way.
packet processing by the host.
Combined
Combined
DMA Path
2
2
Table 22 - DMA Maximum Bandwidths
Packet Size
>1000 bytes
>1000 bytes
>1000 bytes
60 bytes
60 bytes
60 bytes
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
Max Bandwidth Mbps
57
11 (5.5 each way)
58 (29 each way)
6.7
50
60
43
1
Data Sheet