ZL50120 Zarlink, ZL50120 Datasheet - Page 48

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

6.1
A diagram of the ZL5011x device is given in Figure 15, which shows the major data flows between functional
components.
6.2
There are numerous combinations that can be implemented to pass data through the ZL5011x device depending
on the application requirements. The Task Manager can be considered the central pivot, through which all flows
must operate. The Task Manager acts as a “router” in the centre of the chip, directing packets to the appropriate
blocks for further processing. The task message contains a pointer to the relevant data, instructions as to what to
do with the data, and ancillary information about the packet. Effectively this means the flow of data through the
device can be programmed, by setting the task message contents appropriately.
1. This flow is for loopback and may be helpful for test purposes
Block Diagram
Data and Control Flows
Flow Number
10
11
1
2
3
4
5
6
7
8
9
1
1
Table 19 - Standard Device Flows
Data Flows
Control Flows
Recovery
Interface
Figure 15 - ZL50115/16/17/18/19/20 Data and Control Flows
Clock
TDM
TDM to (TM) to PE to (TM) to CPU
Formatter
Assembly
TDM to (TM) to PE to (TM) to PKT
PKT to (TM) to PE to (TM) to TDM
Payload
Control
DMA
TDM
ZL50115/16/17/18/19/20
Motorola PowerQUICC
Flow Through Device
TDM to (TM) to TDM
TDM to (TM) to CPU
CPU to (TM) to TDM
TDM to (TM) to PKT
PKT to (TM) to TDM
PKT to (TM) to CPU
CPU to (TM) to PKT
PKT to (TM) to PKT
Zarlink Semiconductor Inc.
Memory Management Unit
On-chip RAM Controller
Manager
Protocol
Central
Engine
Task
48
Host Interface
TM
Compatible
Transmit
Receive
Packet
Packet
JTAG Interface
JTAG Test
Controller
Interface
Admin.
Packet
MAC
Dual
Data Sheet