ZL50120 Zarlink, ZL50120 Datasheet - Page 36

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

CPU_CS
CPU_WE
CPU_OE
CPU_TS_ALE
CPU_SDACK1
CPU_SDACK2
CPU_CLK
Signal
Table 10 - CPU Interface Package Ball Definition (continued)
I/O
I U
I
I
I
I
I
I
N21
M21
M22
M20
A21
L21
L19
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
36
edge of CPU_CLK and active low. Is
asserted with CPU_TS_ALE. Must be
asserted with CPU_OE to
asynchronously enable the CPU_DATA
output during a read, including DMA
read.
CPU Write Enable. Synchronously
asserted with respect to CPU_CLK
rising edge, and active low. Used for
CPU writes from the processor to
registers within the ZL5011x. Asserted
one clock cycle after CPU_TS_ALE.
CPU Output Enable.
Synchronously asserted with respect to
CPU_CLK rising edge, and active low.
Used for CPU reads from the processor
to registers within the ZL5011x.
Asserted one clock cycle after
CPU_TS_ALE. Must be asserted with
CPU_CS to asynchronously enable the
CPU_DATA output during a read,
including DMA read.
Synchronous input with rising edge of
CPU_CLK.
Latch Enable (ALE), active high signal.
Asserted with CPU_CS, for a single
clock cycle.
CPU/DMA 1 Acknowledge Input. Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL5011x for a DMA write
transaction. Only used for DMA
transfers, not for normal register access.
CPU/DMA 2 Acknowledge Input Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL5011x for a DMA read
transaction. Only used for DMA
transfers, not for normal register access.
CPU PowerQUICC™ II Bus Interface
clock input. 66 MHz clock, with minimum
of 6 ns high/low time. Used to time all
host interface signals into and out of
ZL5011x device.
CPU Chip Select. Synchronous to rising
Description
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