ZL50120 Zarlink, ZL50120 Datasheet - Page 32

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

M0_RBC0
M0_RBC1
M0_COL
M0_RXD[7:0]
M0_RXDV /
M0_RXD[8]
M0_RXER /
M0_RXD[9]
Signal
Table 8 - MII Port 0 Interface Package Ball Definition (continued)
I/O
I U
I U
I D
I U
I D
I D
B9
B8
A7
[7]
[6]
[5]
[4]
C7
D6
A4
A5
D8
A6
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
[3]
[2]
[1]
[0]
MII Port 0
32
C8
D10
C9
B7
TBI - M0_RBC0.
Used as a clock when in TBI mode. Accepts
62.5 MHz and is 180°C out of phase with
M0_RBC1.
each rising edge of M0_RBC1 and
M0_RBC0, resulting in 125 MHz sample
rate.
TBI - M0_RBC1
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180° out of phase with
M0_RBC0. Receive data is clocked at each
rising edge of M0_RBC1 and M0_RBC0,
resulting in 125 MHz sample rate.
GMII/MII - M0_COL.
Collision Detection. This signal is
independent of M0_TXCLK and
M0_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_RXCLK (GMII/MII) or the rising
edges of M0_RBC0 and M0_RBC1 (TBI).
GMII/MII - M0_RXDV
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M0_RXCLK.
It is asserted when valid data is on the
M0_RXD bus.
TBI - M0_RXD[8]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
GMII/MII - M0_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M0_RXDV is asserted. Can be used in
conjunction with M0_RXD when M0_RXDV
signal is de-asserted to indicate a False
Carrier.
TBI - M0_RXD[9]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
Receive data is clocked at
Description
Data Sheet