ZL50120 Zarlink, ZL50120 Datasheet - Page 82

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

12.7
Note 1:
Note 2:
CPU_CLK Period
CPU_CLK High Time
CPU_CLK Low Time
CPU_CLK Rise Time
CPU_CLK Fall Time
CPU_ADDR[23:2] Setup Time
CPU_ADDR[23:2] Hold Time
CPU_DATA[31:0] Setup Time
CPU_DATA[31:0] Hold Time
CPU_CS Setup Time
CPU_CS Hold Time
CPU_WE/CPU_OE Setup Time
CPU_WE/CPU_OE Hold Time
CPU_TS_ALE Setup Time
CPU_TS_ALE Hold Time
CPU_SDACK1/CPU_SDACK2
Setup Time
CPU_SDACK1/CPU_SDACK2
Hold Time
CPU_TA Output Valid Delay
CPU_DREQ0/CPU_DREQ1
Output Valid Delay
CPU_IREQ0/CPU_IREQ1 Output
Valid Delay
CPU_DATA[31:0] Output Valid
Delay
CPU_CS to Output Data Valid
CPU_OE to Output Data Valid
CPU_CLK(falling) to CPU_TA
Valid
CPU Interface Timing
Load = 50 pF maximum
The maximum value of t
how to accommodate this during board design.
Parameter
CTV
may cause setup violations if directly connected to the MPC8260. See Section 14.2 for details of
Table 36 - CPU Timing Specification
Symbol
ZL50115/16/17/18/19/20
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CWV
t
CCH
CCR
CAH
CDS
CDH
CSH
CEH
CKH
CRV
CDV
ODV
CCL
CCF
CAS
CSS
CES
CTS
CTH
CKS
CTV
SDV
OTV
CC
Zarlink Semiconductor Inc.
Min.
3.2
3.3
3.2
6
6
4
2
4
2
4
2
5
2
4
2
2
2
2
2
2
2
82
15.152
Typ.
Max.
10.4
10.4
11.3
9.5
4
4
6
6
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1, 2
Note 1
Note 1
Note 1
Data Sheet
Notes