ZL50120 Zarlink, ZL50120 Datasheet - Page 84

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

CPU_DATA[31:0]
CPU_DATA[31:0]
CPU_SDACK2
CPU_TS_ALE
CPU_DREQ1
CPU_SDACK1
CPU_TS_ALE
CPU_DREQ0
CPU_CLK
CPU_WE
CPU_OE
CPU_CS
CPU_TA
CPU_CLK
Note 1: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid
when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted.
CPU_TA will continue to be driven until CPU_CS is deasserted.
the CPU_DATA output.
Note 2: CPU_DREQ1 shown with postive polarity
CPU_WE
CPU_CS
CPU_OE
CPU_TA
CPU_SDACK2 shown with negative polarity
Note 1: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time.
Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260
will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue
to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and
CPU_DATA may be removed.
Note 2: CPU_DREQ0 shown with positive polarity
CPU_SDACK1 shown with negative polarity
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Figure 42 - CPU DMA Read - MPC8260
Figure 43 - CPU DMA Write - MPC8260
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
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CPU_CS and CPU_OE must BOTH be asserted to enable
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Data Sheet
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