ZL50120 Zarlink, ZL50120 Datasheet - Page 17

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

ZL50120 Package view from TOP side. Note that ball A1 is non-chamfered corner.
AA
AB
W
A
B
C
D
G
H
K
M
N
R
U
E
F
L
P
T
V
Y
J
TDM_CLKI[
TDM_CLKI[
TDM_CLKO
TDM_CLKI[
TDM_STI[0] VDD_IO
M1_TXD[2]
M1_TXD[3]
M1_RXD[1] M1_RXD[0] M1_RXD[2] VDD_IO
M1_RXD[3] M0_GIGABI
TDM_STO[
TDM_STO[
VDD_IO
M_MDIO DEVICE_ID
VDD_IO
M_MDC
GND
1
NC
NC
NC
[2]
IC
IC
IC
3]
2]
2]
1]
0]
AUX_CLKO AUX_CLKI VDD_COR
TDM_CLKO
TDM_STI[1] TDM_CLKI[
TDM_CLKO
TDM_CLKO
TDM_STO[
TDM_CLKI
M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C
M1_CRS DEVICE_ID
VDD_IO
VDD_IO
T_LED
_REF
GND
GND
GND
GND
2
NC
NC
[0]
[3]
[1]
[0]
3]
IC
TDM_STI[3] VDD_IO
TDM_STI[2] VDD_COR
TDM_CLKO
M1_TXCLK M1_RXER
TDM_FRMI
M0_LINKU
TDM_FRM
VDD_IO M1_RXCLK M1_COL
VDD_IO
VDD_IO
O_REF
P_LED
_REF
_REF
GND
GND
GND
NC
NC
NC
3
[1]
0]
IC
M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER
VDD_COR
VDD_COR
VDD_COR
VDD_COR
TDM_STO[
TDM_CLKi
TDM_CLKi
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
4
IC
IC
E
E
E
E
E
E
1]
S
P
M1_RXDV M0_RXER
VDD_IO
VDD_IO
GND
5
IC
VDD_COR
VDD_COR
Figure 7 - ZL50120 Package View and Ball Positions
M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0]
6
IC
IC
E
E
VDD_IO M0_RXD[5] VDD_COR
VDD_IO
GND
7
IC
IC
ZL50115/16/17/18/19/20
A1VDD_PL
VDD_IO
8
LK
IC
L1
IC
VDD_COR
M0_TXEN DEVICE_ID
PLL_PRI
GPIO[0]
GND
GND
GND
GND
GND
GND
Zarlink Semiconductor Inc.
9
IC
E
E
M0_RXD[2] M0_REFCL
PLL_SEC
GPIO[3]
10
GND
GND
GND
GND
GND
GND
[4]
IC
IC
CPU_DATA[
SYSTEM_D
IC_GND
IC_GND
GPIO[4]
17
11
EBUG
GND
GND
GND
GND
GND
GND
GND
28]
K
CPU_DATA[
SYSTEM_R
M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV
M0_TXD[6] M0_TXD[1] VDD_COR
GPIO[5]
12
GND
GND
GND
GND
GND
GND
GND
24]
ST
IC
SYSTEM_C
GPIO[1]
GPIO[6]
13
GND
GND
GND
GND
GND
GND
GND
GND
LK
CPU_DATA[
VDD_COR
GPIO[10]
VDD_IO
GPIO[2]
14
GND
GND
GND
GND
GND
GND
GND
23]
E
E
VDD_COR
GPIO[11]
VDD_IO CPU_DATA[
GPIO[9]
GPIO[8]
GPIO[7]
E_LED
15
GND
E
CPU_DATA[
CPU_DATA[
GPIO[14] TEST_MOD
GPIO[12] TEST_MOD
GPIO[13] TEST_MOD
VDD_IO
VDD_IO
16
19]
27]
31]
CPU_DATA[
CPU_DATA[
M1_LINKU
M0_ACTIV
GPIO[15] DEVICE_ID
P_LED
E_LED
17
E[1]
E[0]
E[2]
12]
22]
CPU_DATA[
CPU_DATA[
CPU_DATA[
VDD_COR
JTAG_TRS
JTAG_TDI
IC_GND
18
20]
29]
[2]
9]
E
T
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_DATA[
DEVICE_ID
VDD_COR
VDD_COR
VDD_COR
VDD_COR
CPU_ADD
CPU_CLK
IC_GND
IC_GND
VDD_IO CPU_DATA[
VDD_IO
VDD_IO
VDD_IO
VDD_IO
19
GND
GND
GND
R[2]
13]
26]
30]
10]
[3]
8]
E
E
E
E
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_IREQ
CPU_TS_A
JTAG_TMS CPU_ADDR
JTAG_TCK CPU_ADDR
JTAG_TDO CPU_ADDR
CPU_ADD
CPU_ADD
CPU_ADD
CPU_ADD
VDD_IO
VDD_IO CPU_ADDR
VDD_IO
Data Sheet
20
R[22]
R[17]
R[11]
GND
GND
GND
R[3]
25]
21]
18]
LE
7]
1]
5]
2]
1
CPU_ADDR
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_ADDR
CPU_ADDR
CPU_ADDR
CPU_SDAC
CPU_SDAC
CPU_WE
CPU_CS CPU_ADDR
VDD_IO
VDD_IO CPU_ADDR
21
GND
GND
[23]
[18]
[13]
[14]
[15]
[10]
15]
17]
11]
K1
IC
K2
[4]
[5]
4]
3]
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_DATA[
CPU_ADDR
CPU_ADDR
CPU_ADDR
CPU_ADDR
CPU_ADDR
CPU_ADDR
CPU_ADDR
CPU_IREQ
IC_VDD_IO
CPU_DRE
CPU_DRE
CPU_TA
CPU_OE
VDD_IO
VDD_IO
22
[19]
[21]
[20]
[16]
[12]
Q1
14]
16]
Q0
IC
[9]
[8]
[7]
[6]
6]
0]
0