dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet - Page 82

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dsp56800eerm

Manufacturer Part Number
dsp56800eerm
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
5.6.2.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2.2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
5.6.2.3
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
5.6.2.4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
5.6.3
82
Base + $2
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
RESET
Write
Read
Interrupt Priority Register 2 (IPR2)
Reserved—Bits 15–6
EOnCE Receive Register Full Interrupt Priority Level
(RX_REG IPL)—Bits 5–4
EOnCE Transmit Register Empty Interrupt Priority Level
(TX_REG IPL)—Bits 3–2
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)—
Bits 1–0
FMCBE IPL
15
0
14
0
Figure 5-5 Interrupt Priority Register 2 (IPR2)
13
FMCC IPL
0
12
0
56F8357 Technical Data, Rev. 15
FMERR IPL
11
0
10
0
LOCK IPL
9
0
8
0
7
0
LVI IPL
6
0
5
0
0
4
0
0
3
IRQB IPL
0
Freescale Semiconductor
2
0
1
IRQA IPL
0
Preliminary
0
0

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