dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet - Page 41

• Manufacturer Part Number: dsp56800eerm
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.2.3
The recommended method of connecting an external clock is given in
source is connected to XTAL and the EXTAL pin is grounded. When using an external clock source, set
the OCCS_COHL bit high as well.
3.3 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions without the internal Relaxation Oscillator, since the 56F8357/56F8157 do NOT
contain this oscillator.
Part 4 Memory Map
4.1 Introduction
The 56F8357 and 56F8157 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memory are used in both spaces.
This chapter provides memory maps for:
On-chip memory sizes for each device are summarized in
identified in the “Use Restrictions” column of
Note: Data Flash and Program RAM are NOT available on the 56F8157 device.
Freescale Semiconductor
Preliminary
Program Flash
Data Flash
Program RAM
Data RAM
Program Boot Flash
On-Chip Memory
•
•
Program Address Space including the Interrupt Vector Table
Data Address Space including the EOnCE Memory and Peripheral Memory Maps
External Clock Source
56F8357
External
256KB
Figure 3-4 Connecting an External Clock Signal
16KB
16KB
XTAL
Clock
8KB
4KB
Table 4-1 Chip Memory Configurations
EXTAL
V
56F8157
SS
256KB
16KB
16KB
56F8357 Technical Data, Rev. 15
—
—
Note: When using an external clocking source with
this configuration, the input “CLKMODE” should be
high and the COHL bit in the OSCTL register
should be set to 1.
Table
Erase / Program via Flash interface unit and word writes to CDBW
Erase / Program via Flash interface unit and word writes to CDBW.
Data Flash can be read via one of CDBR or XDB2, but not both
simultaneously
None
None
Erase / Program via Flash Interface unit and word to CDWB
4-1.
Table
4-1. Flash memories’ restrictions are
Use Restrictions
Figure
3-4. The external clock
Registers
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