dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet - Page 144

• Manufacturer Part Number: dsp56800eerm
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
144
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
RESET Assertion to Address, Data and
Control Signals High Impedance
Minimum RESET Assertion Duration
RESET Deassertion to First External Address
Output
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data
Memory Access Out Valid, caused by first
instruction execution in the interrupt service
routine
IRQA, IRQB Assertion to General Purpose
Output Valid, caused by first instruction
execution in the interrupt service routine
Delay from IRQA Assertion (exiting Wait) tto
External Data Memory Access
Delay from IRQA Assertion to External Data
Memory Access (exiting Stop)
IRQA Width Assertion to Recover from Stop
State
Stop modes), T = 125ns.
This is not the minimum required so that the IRQA interrupt is accepted.
5
3
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Characteristic
4
56F8357 Technical Data, Rev. 15
t
IDM
t
t
t
IG
IRI
IF
Symbol
t
t
- FAST
t
t
- FAST
t
RDA
-FAST
RAZ
IRW
t
t
IDM
- FAST
t
t
RA
IRI
IW
IG
IF
Typical
1.5T
1.5T
Min
16T
63T
18T
14T
18T
14T
22T
18T
—
—
—
Typical
Max
64T
21
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
1,2
See Figure
10-5
10-5
10-5
10-6
10-7
10-7
10-8
10-9
10-9
21
Preliminary
T.