dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet - Page 4

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dsp56800eerm

Manufacturer Part Number
dsp56800eerm
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
56F8357/56F8157 General Description
Note: Features in italics are NOT available in the 56F8157 device.
4
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
• Access up to 4MB of off-chip program and 32MB of
• Chip Select Logic for glueless interface to ROM and
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
C-efficient architecture
data memory
SRAM
4
3
4
4
4
5
4
4
3
4
4
2
4
2
6
6
SPI1 or GPIOC
Current Sense Inputs or GPIOC
Current Sense Inputs or GPIOD
VREF
TEMP_SENSE
PWM Outputs
Fault Inputs
PWM Outputs
Fault Inputs
AD0
AD1
Decoder 0 or
AD0
AD1
Decoder 1 or
Quadrature
Quadrature
Timer D or
Timer B or
Timer C or
Timer or /
FlexCAN
GPIOC
GPIOE
GPIOE
Quad
Quad
Quad
Quad
ADCA
ADCB
Decoding
Peripherals
SPI0 or
Program Memory
GPIOE
128K x 16 Flash
4K x 16 Flash
Data Memory
8K x 16 RAM
2K x 16 RAM
Boot Flash
Memory
4
8K x 16
PWMA
PWMB
SCI1 or
GPIOD
2
SCI0 or
GPIOE
RSTO
Hardware Looping Unit
2
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
Program Controller
RESET
Watchdog
56F8357/56F8157 Block Diagram
EMI_MODE
COP/
and
Device Selects
EXTBOOT
Peripheral
56F8357 Technical Data, Rev. 15
PAB
PDB
CDBR
CDBW
EOnCE
JTAG/
Generation Unit
Port
IPBus Bridge (IPBB)
IRQA
Address
5
Controller
Interrupt
RW
Control
V
2
PP
IRQB
56800E Core
IPAB
16-Bit
V
4
CAP
System Bus
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
• Up to 76 GPIO lines
• 160-pin LQFP Package and 160MAPBGA
Three 16-bit Input Registers
16 x 16 + 36 -> 36-Bit MAC
Four 36-bit Accumulators
IPWDB
Control
7
unobtrusive, real-time debugging
V
DD
Digital Reg
OCR_DIS
Data ALU
IPRDB
System
Integration
Module
6
Low Voltage
V
Supervisor
SS
R/W Control
CLKO
Clock
resets
V
2
Analog Reg
DDA
O
R
P
CLKMODE
V
Generator
Manipulation
SSA
Clock
Unit
Bit
External Data
Address Bus
PLL
Bus Control
Bus Switch
External
Switch
O
C
S
XTAL
EXTAL
Freescale Semiconductor
6
2
8
4
1
3
7
9
6
shown for on-chip
* Configuration
2.5V regulator
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
**See Table 2-2
for explanation
Preliminary

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