dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet - Page 121

• Manufacturer Part Number: dsp56800eerm
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

6.5.10.1
This field represents the upper two address bits of the “hard coded” I/O short address.
6.5.10.2
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut
down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and
master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused.
Clock enables provide the means to disable individual clocks. Some peripherals provide further controls
to disable unused subfunctions. Refer to
Peripheral User Manual for further details.
6.7 Power Down Modes Overview
The 56F8357/56F8157 operate in one of three power-down modes as shown in
Freescale Semiconductor
Preliminary
Base + $D
Base + $E
RESET
RESET
Write
Write
Read
Read
Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
Figure 6-15 I/O Short Address Location Low Register (SIM_ISAL)
15
15
1
1
1
14
14
1
1
1
13
13
1
1
1
12
12
1
1
1
56F8357 Technical Data, Rev. 15
11
11
1
1
1
Part 3 On-Chip Clock Synthesis
10
10
1
1
1
9
1
1
9
1
8
8
1
1
1
ISAL[21:6]
7
7
1
1
1
6
6
1
1
1
5
5
1
1
1
4
4
1
1
1
(OCCS), and the 56F8300
Table 6-3
3
3
1
1
1
Clock Generation Overview
2
2
1
1
1
.
ISAL[23:22]
1
1
1
1
0
0
1
1
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