dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet - Page 114

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dsp56800eerm

Manufacturer Part Number
dsp56800eerm
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
The upper four bits of the GPIOB register can function as GPIO, A[23:A20], or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed
to operate as peripheral outputs, then the choice between A[23:A20] and additional clock outputs is done
here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as
A[23:A20]. This can be changed by altering A[23:A20] as shown in
6.5.7.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7.2
6.5.7.3
6.5.7.4
6.5.7.5
6.5.7.6
114
Base + $A
RESET
0 = Peripheral output function of GPIOB7 is defined to be A23
1 = Peripheral output function of GPIOB7 is defined to be the oscillator clock (MSTR_OSC in
0 = Peripheral output function of GPIOB6 is defined to be A22
1 = Peripheral output function of GPIOB6 is defined to be SYS_CLK2
0 = Peripheral output function of GPIOB5 is defined to be A21
1 = Peripheral output function of GPIOB5 is defined to be SYS_CLK
0 = Peripheral output function of GPIOB4 is defined to be A20
1 = Peripheral output function of GPIOB4 is defined to be the prescaler clock (FREF in
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated
Read
Write
Reserved—Bits 15–10
Alternate GPIOB Peripheral Function for A23 (A23)—Bit 9
Alternate GPIOB Peripheral Function for A22 (A22)—Bit 8
Alternate GPIOB Peripheral Function for A21 (A21)—Bit 7
Alternate GPIOB Peripheral Function for A20 (A20)—Bit 6
Clockout Disable (CLKDIS)—Bit 5
15
0
0
14
0
0
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
13
0
0
12
0
0
56F8357 Technical Data, Rev. 15
11
0
0
10
0
0
A23
9
0
A22
8
0
A21
7
0
A20
6
0
Figure
CLK
DIS
5
1
6-9.
4
0
3
0
Freescale Semiconductor
CLKOSEL
Figure
2
0
1
0
Figure
3-4)
Preliminary
0
0
3-4)

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