dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet - Page 122

• Manufacturer Part Number: dsp56800eerm
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
6.8 Stop and Wait Mode Disable Function
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest
power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering
Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E
system clock must be set equal to the oscillator output.
122
Run
Wait
Stop
Mode
Active
Core and memory
clocks disabled
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
Permanent
Disable
Clock
Select
Reprogrammable
Disable
Core Clocks
Table 6-3 Clock Operation in Power Down Modes
Figure 6-16 Stop Disable Circuit
Active
Active
Peripheral Clocks
Reset
56F8357 Technical Data, Rev. 15
D
D-FLOP
C
D
D-FLOP
C
R
Device is fully functional
Peripherals are active and can produce interrupts if they
have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
Q
Q
Note: Wait disable circuit
is similar
Description
STOP_DIS
56800E
Freescale Semiconductor
Preliminary