dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet - Page 140

• Manufacturer Part Number: dsp56800eerm
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

10.5 External Clock Operation Timing
10.6 Phase Locked Loop Timing
140
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
1. Parameters listed are guaranteed by design.
2. See
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
Frequency of operation (external clock driver)
Clock Pulse Width
External clock input rise time
External clock input fall time
correctly. The PLL is optimized for 8MHz input crystal.
the 56F8300 Peripheral User Manual.
External
Note: The midpoint is V
Clock
Figure 10-3
Table 10-13 External Clock Operation Timing Requirements
Characteristic
Characteristic
for details on using the recommended connection of an external clock driver.
3
10%
50%
90%
2
3
(f
-40° to +125°C
OUT
t
PW
IL
)
5
4
+ (V
Figure 10-3 External Clock Timing
IH
– V
IL
56F8357 Technical Data, Rev. 15
Table 10-14 PLL Timing
)/2.
2
t
PW
1
f
t
t
t
Symbol
osc
PW
rise
fall
Symbol
f
t
f
osc
plls
op
Min
3.0
—
—
0
OUT
Min
160
t
—
fall
4
/2
)
, please refer to the OCCS chapter in
Typ
—
—
—
—
Typ
—
8
1
t
rise
Max
Freescale Semiconductor
Max
120
260
8.4
10
10
—
10
1
10%
50%
90%
MHz
V
V
Unit
MHz
MHz
Unit
ns
ns
ns
ms
IH
IL
Preliminary