dsp56800eerm Freescale Semiconductor, Inc, dsp56800eerm Datasheet
dsp56800eerm
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dsp56800eerm Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8357 Rev. 15 01/2007 freescale.com ...
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Version History Rev 1.0 Initial Public Release Rev 2.0 Added Package Pins to GPIO Table in “Typical Min” values to family. Updated values in Regulator Parameters Requirements Coefficients at 10MHz Rev 3.0 Corrected Table 4-6 Rev 4.0 Added Part 4.8, ...
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Document Revision History (Continued) Version History • Added the following note to the description of the TMS signal in Rev. 15 Note: Always tie the TMS pin to V • Added the following note to the description of the TRST ...
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General Description Note: Features in italics are NOT available in the 56F8157 device. • MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 4MB of off-chip ...
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Part 1: Overview 1.1. 56F8357/56F8157 Features . . . . . . . . . . . ...
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Part 1 Overview 1.1 56F8357/56F8157 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Million Instructions Per Second (MIPS MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) ...
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Memory Note: Features in italics are NOT available in the 56F8157 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection feature • On-chip memory, including a low-cost, high-volume ...
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Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) • Two Serial Peripheral Interfaces (SPIs). both with configurable 4-pin port (or eight additional GPIO lines); SPI1 can also be used as Quadrature Decoder 1 ...
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Features The 56F8357 controller includes 256KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. It also supports program execution from external memory. ...
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A key application-specific feature of the 56F8157 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control ...
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Architecture Block Diagram Note: Features in italics are NOT available in the 56F8157 device and are shaded in the following figures. The 56F8357/56F8157 architecture is shown in 56800E system buses communicate with internal memories, the external memory interface and ...
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JTAG / EOnCE cdbw_m[31:0] 56800E CHIP TAP Controller TAP Linking Module External JTAG Port cdbr_m[31:0] xdb2_m[15:0] NOT available on the 56F8157 device. Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is accomplished by the ...
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CLKGEN (OSC/PLL) Timer A 4 Quadrature Decoder 0 4 Timer D Timer B 4 Quadrature Decoder NOT available on the 56F8157 device. Freescale Semiconductor Preliminary To/From IPBus Bridge SPI 1 GPIO A GPIO B GPIO C ...
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Name pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory ...
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... Freescale Literature Distribution Table 1-3 Chip Documentation Description Logic State True False True False 56F8357 Technical Data, Rev. 15 Product Documentation Centers, or online Order Number DSP56800EERM MC56F8300UM MC56F83xxBLUM MC56F8357 MC56F8357E MC56F8157E Signal State 1 Voltage Asserted Deasserted V /V ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8357 and 56F8157 are organized into functional groups, as detailed in Table 2-1 and as illustrated in present on a pin. Table 2-1 Functional Group Pin Allocations ...
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Power V DDA_OSC_PLL Power V DDA_ADC Power Ground V SSA_ADC Ground OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL and Clock (GPIOA8 - 13 (GPIOE2 - ...
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Power V DDA_OSC_PLL Power V Power Ground V Ground OCR_DIS Other CAP Supply V PP Ports CLKMODE PLL and Clock (GPIOA8 - 13 (GPIOE2 - A15 (GPIOA0 ...
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Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Note: Signals in italics are NOT available in the 56F8157 device. Note: The 160 Map Ball Grid Array is ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No K11 G11 125 J11 SS V 160 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. XTAL 93 K12 CLKO 154 C3 (GPIOA8 (GPIOA9 (GPIOA10 (GPIOA11) ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No (GPIOE2 (GPIOE3 (GPIOA0 (GPIOA1) A10 21 H2 (GPIOA2) A11 22 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. GPIOB0 33 L1 (A16) GPIOB1 34 L3 (A17) GPIOB2 35 L2 (A18) GPIOB3 36 M1 (A19) GPIOB4 37 M2 (A20) (prescaler_ clock) ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No P10 (GPIOF9 N10 (GPIOF10 P14 (GPIOF11 L13 (GPIOF12 L14 (GPIOF13 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No (GPIOF0 (GPIOF1 (GPIOF2) D10 32 K4 (GPIOF3) D11 149 A5 (GPIOF4) D12 150 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No (CS0) (GPIOD8 (CS1) (GPIOD9) 26 State Type During Reset Output In reset, Write ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. GPIOD0 55 P6 (CS2) GPIOD1 56 L6 (CS3) GPIOD2 57 K6 (CS4) GPIOD3 58 N7 (CS5) GPIOD4 59 P7 (CS6) GPIOD5 60 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. TXD1 49 P4 (GPIOD6) RXD1 50 N5 (GPIOD7) TCK 137 D8 TMS 138 A8 TDI 139 B8 TDO 140 D7 28 State ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. TRST 136 D9 PHASEA0 155 A2 (TA0) (GPIOC4) PHASEB0 156 B4 (TA1) (GPIOC5) Freescale Semiconductor Preliminary State Type During Reset Schmitt Input, ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. INDEX0 157 A1 (TA2) (GPIOC6) HOME0 158 B3 (TA3) (GPIOC7) SCLK0 146 A6 (GPIOE4) 30 State Type During Reset Schmitt Input, Index ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. MOSI0 148 B6 (GPIOE5) MISO0 147 D4 (GPIOE6) SS0 145 D5 (GPIOE7) Freescale Semiconductor Preliminary State Type During Reset Input/ In reset, ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. PHASEA1 6 C1 (TB0) (SCLK1) (GPIOC0) PHASEB1 7 D1 (TB1) (MOSI1) (GPIOC1) 32 State Type During Reset Schmitt Input, Phase A1 — ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. INDEX1 8 E2 (TB2) (MISO1) (GPIOC2) HOME1 9 E1 (TB3) (SS1) (GPIOC3) Freescale Semiconductor Preliminary State Type During Reset Schmitt Input, Index1 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. PWMA0 73 M11 PWMA1 75 P12 PWMA2 76 N11 PWMA3 78 M12 PWMA4 79 P13 PWMA5 81 N12 ISA0 126 A11 (GPIOC8) ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. ISB0 61 N8 (GPIOD10) ISB1 63 L8 (GPIOD11) ISB2 64 P8 (GPIOD12) FAULTB0 67 N9 FAULTB1 68 L9 FAULTB2 69 L10 FAULTB3 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. ANB0 116 C13 ANB1 117 B14 ANB2 118 C12 ANB3 119 B13 ANB4 120 A14 ANB5 121 A13 ANB6 122 B12 ANB7 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. TD0 129 B10 (GPIOE10) TD1 130 A10 (GPIOE11) TD2 131 D10 (GPIOE12) TD3 132 E10 (GPIOE13) IRQA 65 K9 IRQB 66 P9 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Pin Ball No. Name No. EXTBOOT 124 B11 EMI_MODE 159 B2 38 State Type During Reset Schmitt Input, External Boot — This input is tied to V ...
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Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. specific OCCS ...
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The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. ...
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External Clock Source The recommended method of connecting an external clock is given in source is connected to XTAL and the EXTAL pin is grounded. When using an external clock source, set the OCCS_COHL bit high as well. XTAL ...
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Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in map configurations that are possible at reset. After reset, ...
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Table 4-4 Program Memory Map at Reset Mode 0 ( Begin/End Internal Boot Address Internal Boot 16-Bit External Address Bus P:$1F FFFF External Program Memory P:$10 0000 P:$0F FFFF P:$03 0000 P:$02 FFFF P:$02 F800 P:$02 F7FF P:$02 ...
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Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the 56F8157 device. Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level core 2 3 core 3 3 core 4 3 core ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level GPIOB 34 0-2 GPIOA 35 0-2 SPI1 38 0-2 SPI1 39 0-2 SPI0 40 0-2 SPI0 41 0-2 SCI1 42 0-2 SCI1 43 0-2 SCI1 45 0-2 SCI1 46 ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level ADCA 74 0-2 ADCB 75 0-2 ADCA 76 0-2 PWMB 77 0-2 PWMA 78 0-2 PWMB 79 0-2 PWMA 80 0-2 core Two words are ...
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Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by ...
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Flash Size Program Flash 256KB Data Flash Boot Flash 16KB Please see 56F8300 Peripheral User Manual for additional Flash information. 4.6 EOnCE Memory Map Address Register Acronym X:$FF FF8A OESCR X:$FF FF8E OBCNTR X:$FF FF90 OBMSK (32 bits) X:$FF FF91 ...
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Table 4-8 EOnCE Memory Map (Continued) Address Register Acronym X:$FF FFFD OTXRXSR (8 bits) X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFF OTX1 / ORX1 4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory ...
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Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral SPI #0 SPI #1 COP PLL, OSC GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E GPIO Port F SIM Power Supervisor FM ...
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Table 4-10 External Memory Integration Registers Address Map (Continued) Register Acronym Address Offset CSOR 0 $8 CSOR 1 $9 CSOR 2 $A CSOR 3 $B CSOR 4 $C CSOR 5 $D CSOR 6 $E CSOR 7 $F CSTC 0 $10 ...
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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD ...
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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSCR Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in the 56F8157 device Register Acronym TMRB0_CMP1 TMRB0_CMP2 TMRB0_CAP TMRB0_LOAD ...
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Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8157 device Register Acronym TMRB2_CMP1 TMRB2_CMP2 TMRB2_CAP TMRB2_LOAD TMRB2_HOLD TMRB2_CNTR TMRB2_CTRL TMRB2_SCR TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP TMRB3_LOAD TMRB3_HOLD TMRB3_CNTR TMRB3_CTRL TMRB3_SCR ...
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Table 4-13 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 TMRC3_CMP2 ...
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Table 4-13 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Table 4-14 Quad Timer D Registers Address Map Quad Timer D is NOT available in the 56F8157 device Register Acronym TMRD0_CMP1 TMRD0_CMP2 ...
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Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8157 device Register Acronym TMRD1_COMSCR TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR TMRD2_CMPLD1 TMRD2_CMPLD2 TMRD2_COMSCR TMRD3_CMP1 TMRD3_CMP2 TMRD3_CAP TMRD3_LOAD TMRD3_HOLD TMRD3_CNTR TMRD3_CTRL ...
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Table 4-15 Pulse Width Modulator A Registers Address Map PWMA is NOT available in the 56F8157 device Register Acronym PWMA_PMCTL PWMA_PMFCTL PWMA_PMFSA PWMA_PMOUT PWMA_PMCNT PWMA_PWMCM PWMA_PWMVAL0 PWMA_PWMVAL1 PWMA_PWMVAL2 PWMA_PWMVAL3 PWMA_PWMVAL4 PWMA_PWMVAL5 PWMA_PMDEADTM PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Table 4-16 ...
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Table 4-16 Pulse Width Modulator B Registers Address Map (Continued) Register Acronym PWMB_PWMVAL1 PWMB_PWMVAL2 PWMB_PWMVAL3 PWMB_PWMVAL4 PWMB_PWMVAL5 PWMB_PMDEADTM PWMB_PMDISMAP1 PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Table 4-17 Quadrature Decoder 0 Registers Address Map Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV ...
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Table 4-18 Quadrature Decoder 1 Registers Address Map Quadrature Decoder 1 is NOT available in the 56F8157 device Register Acronym DEC1_DECCR DEC1_FIR DEC1_WTR DEC1_POSD DEC1_POSDH DEC1_REV DEC1_REVH DEC1_UPOS DEC1_LPOS DEC1_UPOSH DEC1_LPOSH DEC1_UIR DEC1_LIR DEC1_IMR Table 4-19 Interrupt Control Registers Address ...
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Table 4-19 Interrupt Control Registers Address Map (Continued) Register Acronym FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 IRQP 2 IRQP 3 IRQP 4 IRQP 5 ICTL Table 4-20 Analog-to-Digital Converter Registers Address Map Register Acronym ADCA_CR 1 ADCA_CR 2 ADCA_ZCC ...
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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_LLMT 2 ADCA_LLMT 3 ADCA_LLMT 4 ADCA_LLMT 5 ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ADCA_HLMT 4 ADCA_HLMT 5 ADCA_HLMT 6 ADCA_HLMT 7 ADCA_OFS 0 ...
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Table 4-21 Analog-to-Digital Converter Registers Address Map Register Acronym ADCB_CR 1 ADCB_CR 2 ADCB_ZCC ADCB_LST 1 ADCB_LST 2 ADCB_SDIS ADCB_STAT ADCB_LSTAT ADCB_ZCSTAT ADCB_RSLT 0 ADCB_RSLT 1 ADCB_RSLT 2 ADCB_RSLT 3 ADCB_RSLT 4 ADCB_RSLT 5 ADCB_RSLT 6 ADCB_RSLT 7 ADCB_LLMT 0 ...
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Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCB_HLMT 5 ADCB_HLMT 6 ADCB_HLMT 7 ADCB_OFS 0 ADCB_OFS 1 ADCB_OFS 2 ADCB_OFS 3 ADCB_OFS 4 ADCB_OFS 5 ADCB_OFS 6 ADCB_OFS 7 ADCB_POWER ADCB_CAL Table 4-22 Temperature Sensor Register Address ...
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Table 4-24 Serial Communication Interface 1 Registers Address Map Register Acronym SCI1_SCIBR SCI1_SCICR SCI1_SCISR SCI1_SCIDR Table 4-25 Serial Peripheral Interface 0 Registers Address Map Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Table 4-26 Serial Peripheral Interface 1 Registers Address Map Register ...
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Table 4-28 Clock Generation Module Registers Address Map Register Acronym PLLCR PLLDB PLLSR SHUTDOWN OSCTL Table 4-29 GPIOA Registers Address Map Address Offset Register Acronym GPIOA_PUR $0 GPIOA_DR $1 GPIOA_DDR $2 GPIOA_PER $3 GPIOA_IAR $4 GPIOA_IENR $5 GPIOA_IPOLR $6 GPIOA_IPR ...
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Table 4-30 GPIOB Registers Address Map (Continued) Register Acronym Address Offset GPIOB_IAR $4 GPIOB_IENR $5 GPIOB_IPOLR $6 GPIOB_IPR $7 GPIOB_IESR $8 GPIOB_PPMODE $9 GPIOB_RAWDATA $A Table 4-31 GPIOC Registers Address Map Register Acronym GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR ...
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Table 4-32 GPIOD Registers Address Map Register Acronym Address Offset GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA Table 4-33 GPIOE Registers Address Map Register Acronym Address Offset GPIOE_PUR GPIOE_DR GPIOE_DDR GPIOE_PER GPIOE_IAR GPIOE_IENR GPIOE_IPOLR GPIOE_IPR GPIOE_IESR ...
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Table 4-34 GPIOF Registers Address Map Register Acronym GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR GPIOF_PPMODE GPIOF_RAWDATA Table 4-35 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS ...
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Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Table 4-37 Flash Module Registers Address Map Register Acronym FMCLKD FMMCR FMSECH FMSECL FMPROT FMPROTB FMUSTAT FMCMD FMOPT 0 FMOPT 1 FMOPT 2 70 (LVI_BASE = $00 F360) Address ...
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Table 4-38 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8157 device Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR FCMAXMB FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8157 device Register Acronym FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8157 device Register Acronym FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8157 device Register Acronym FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB12_CONTROL FCMB12_ID_HIGH ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8157 device Register Acronym FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA Freescale Semiconductor ...
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Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application can be used to load a user application into the Program and Data Flash (NOT available in ...
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Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition 1 ...
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Block Diagram Priority Level 2->4 INT1 Decode Priority Level 2->4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ITCN is in this ...
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Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has ...
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Add. Register Offset Name IPR0 BKPT_U0 IPL IPR1 IPR2 FMCBE IPL FMCC IPL W R GPIOD $3 IPR3 IPL IPR4 SPI0_RCV ...
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Interrupt Priority Register 0 (IPR0) Base + $ Read 0 0 BKPT_U0IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It ...
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Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the ...
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Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. ...
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Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ ...
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GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) ...
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FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) ...
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SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SPI0 Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
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Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled ...
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Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
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Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
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ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Fast interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5. ...
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Reserved—Bits 15–7 This bit field is reserved or not implemented read as 0, but cannot be modified by writing. 5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0 This value determines which IRQ will be a ...
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IRQ Pending 0 Register (IRQP0) Base + $ Read Write RESET Figure 5-20 IRQ Pending 0 Register (IRQP0) 5.6.18.1 IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the ...
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IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for ...
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IRQ Pending 5 Register (IRQP5) Base + $ Read Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits 96–82 This bit field is reserved or not implemented. The ...
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Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • interrupt is being sent to the 56800E core • interrupt is being sent to the 56800E ...
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IRQA Edge Pin (IRQA Edg)—Bit 0 This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes automatically level-sensitive. • IRQA interrupt is a low-level sensitive (default) • 1 ...
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Part 6 System Integration Module (SIM) 6.1 Overview The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system ...
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Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and ...
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Register Descriptions Address Offset Address Acronym Base + $0 SIM_CONTROL Base + $1 SIM_RSTSTS Base + $2 SIM_SCR0 Base + $3 SIM_SCR1 Base + $4 SIM_SCR2 Base + $5 SIM_SCR3 Base + $6 SIM_MSH_ID Base + $7 SIM_LSH_ID Base ...
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Add. Register Offset Name SIM_ $0 CONTROL SIM_ $1 RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ ...
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EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can ...
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Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.2.2 Software Reset (SWR)—Bit 5 When 1, this bit indicates that the previous reset occurred as a result ...
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Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the ...
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Reserved—Bit 15 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.2 PWMA1—Bit 14 This bit controls the pull-up resistors on the FAULTA3 pin. 6.5.6.3 CAN—Bit 13 This bit ...
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The upper four bits of the GPIOB register can function as GPIO, A[23:A20 additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed to operate as peripheral outputs, then the choice ...
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CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin. • 00000 = SYS_CLK (from OCCS - DEFAULT) • 00001 = Reserved for factory test—56800E clock • 00010 = Reserved for factory test—XRAM clock • ...
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Quad Timer Controlled SPI Controlled Figure 6-10 Overall Control of Pads Using SIM_GPS Control Table 6-2 Control of Pads Using SIM_GPS Control Pin Function GPIO Input 0 GPIO Output 0 Quad Timer Input / 1 2 Quad Decoder Input Quad ...
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Base + $ Read Write RESET Figure 6-11 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–4 This bit field is reserved or not implemented read as 0 and cannot ...
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Base + $ Read EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC Write RESET Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) 6.5.9.1 External Memory Interface Enable (EMI)—Bit 15 Each bit controls clocks to the ...
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Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 Quad Timer C ...
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Pulse Width Modulator B Enable (PWMB)—1 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 Pulse Width Modulator ...
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Base + $ Read Write RESET Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of ...
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Table 6-3 Clock Operation in Power Down Modes Mode Core Clocks Run Active Wait Core and memory clocks disabled Stop System clocks continue to be generated in the SIM, but most are gated prior to reaching memory, core and peripherals. ...
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Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL), described in can be on either a permanent or temporary basis. Permanently assigned applications last only until their ...
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Flash Access Blocking Mechanisms The 56F8357/56F8157 have several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Methods ...
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The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides down the system clock for timed events, as illustrated in PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of ...
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TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 ...
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Table 8-1 56F8357 GPIO Ports Configuration Available GPIO Port Pins in Port Width 56F8347 pins - EMI Address pins pins - EMI Address pins pins -DEC1 / TMRB ...
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Table 8-3 GPIO External Signals Map Pins in italics are NOT available in the 56F8157 device GPIO Port GPIOA GPIOB 1 This is a function of the EMI_MODE, EXTBOOT and Flash security settings at reset. 128 Reset GPIO Bit Function ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8157 device GPIO Port GPIOC GPIOD Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 Peripheral PhaseA1 / TB0 / SCLK1 1 Peripheral PhaseB1 / TB1 ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8157 device GPIO Port GPIOE GPIOF 1. See Part 6.5.8 to determine how to select peripherals from this set 130 Reset GPIO Bit Function 0 ...
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Part 9 Joint Test Action Group (JTAG) 9.1 JTAG Information Please contact your Freescale device/package-specific BSDL information. Part 10 Specifications 10.1 General Characteristics The 56F8357/56F8157 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to ...
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Note: The 56F8157 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8157 device. Table 10-1 Absolute Maximum Ratings Characteristic Supply Voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal Logic Core Supply Voltage ...
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Table 10-2 56F8357/56F8157 ElectroStatic Discharge (ESD) Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Four layer ...
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Note: The 56F8157 device is guaranteed to 40MHz and specified to meet Industrial requirements only. Table 10-4 Recommended Operating Conditions (V = 0V, V REFLO Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal Logic Core Supply ...
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DC Electrical Characteristics Note: The 56F8157 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8157 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Characteristic Symbol V Output High Voltage V ...
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Table 10-6 Power-On Reset Low Voltage Parameters Characteristic POR Trip Point 1 LVI, 2.5 volt Supply, trip point 2 LVI, 3.3 volt supply, trip point Bias Current 1. When V drops below V DD_CORE 2. When V drops below V ...
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Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) I Mode DD_Core RUN1_MAC 150mA Wait3 86mA Stop1 900μA Stop2 100μ Output Switching Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200 ...
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Characteristics PLL Start-up time Resonator Start-up time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8157 device. Table 10-11 Temperature Sense Parametrics Characteristics 1 Slope (Gain) ...
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AC Electrical Characteristics Tests are conducted using the input levels specified in propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in ...
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External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements Characteristic Frequency of operation (external clock driver) 3 Clock Pulse Width 4 External clock input rise time 5 External clock input fall time 1. Parameters listed are guaranteed ...
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Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Bias Current, high-drive mode Bias Current, low-drive mode ...
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DCAOE and DCAEO are calculated as follows: 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 DCAOE = = 0.0 all other cases MIN XTAL duty cycle - 0.5, if ...
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Table 10-16 External Memory Interface Timing Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Data Out Valid to WR Asserted Valid Data Out Hold Time after WR Deasserted Valid Data Out Set-Up Time to WR Deasserted ...
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Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration RESET Deassertion to First External Address ...
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RESET t RAZ A0–A15, D0–D15 PS, DS, RD, WR Figure 10-5 Asynchronous Reset Timing IRQA, IRQB Figure 10-6 External Interrupt Timing (Negative-Edge Sensitive) A0–A15 IDM , IRQA IRQB General Purpose I/O Pin ...
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IRQA, IRQB A0–A15, PS, DS, RD, WR Figure 10-8 Interrupt from Wait State Timing t IW IRQA A0–A15, PS, DS, RD, WR Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 10.10 Serial Peripheral Interface (SPI) Timing Characteristic Cycle ...
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Characteristic Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref) ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-12 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...
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Quad Timer Timing Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period 1. In the formulas listed the clock cycle. For 60MHz operation 16.67ns. 2. ...
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Phase A (Input) Phase B (Input) Figure 10-15 Quadrature Decoder Timing 10.13 Serial Communication Interface (SCI) Timing Characteristic Symbol 2 Baud Rate 3 RXD RXD Pulse Width 4 TXD Pulse Width TXD 1. Parameters listed are guaranteed by design. 2. ...
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Controller Area Network (CAN) Timing Note: CAN is not available in the 56F8157 device. Characteristic Baud Rate Bus Wake Up detection 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin (Input) 10.15 JTAG Timing Characteristic TCK ...
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TCK (Input – Figure 10-19 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-20 Test Access Port Timing Diagram TRST ...
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Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion range ADC channel power-up time ADC reference circuit power-up time Conversion time Sample time Input capacitance 5 Input injection current , ...
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Table 10-24 ADC Parameters (Continued) Characteristic Total Harmonic Distortion Spurious Free Dynamic Range 8 Effective Number Of Bits 1. INL measured from V = .1V in REFH 10% to 90% Input Signal Range 2. LSB = Least Significant Bit 3. ...
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Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken ...
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Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample & hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & open, one ...
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C, the internal [dynamic component], is classic C*V 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly ...
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Part 11 Packaging Note: The 160 Map Ball Grid Array is not available in the 56F8157 device. 11.1 56F8357 Package and Pin-Out Information This section contains package and pin-out information for the 56F8357. This device comes in a 160-pin Low-profile ...
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Table 11-1 56F8357 160-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name DD_IO CLKO 43 4 TXD0 44 5 RXD0 45 6 PHASEA1 46 7 PHASEB1 47 ...
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Table 11-1 56F8357 160-Pin LQFP Package Identification by Pin Number (Continued) Signal Pin No. Pin No. Name 26 A15 DD_IO 32 D10 72 ...
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A INDEX0 D15 PHASEA0 B EMI_ HOME0 PHASEB0 TXD0 MODE PHASEA1 RXD0 PHASEB1 CLKO MISO0 E HOME1 INDEX1 ...
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Table 11-2 56F8357 -160 MAPBGA Package Identification by Pin Number Ball Ball Signal Name No. No K11 DD_IO CLKO N3 B1 TXD0 P2 D2 RXD0 M3 C1 PHASEA1 N4 D1 PHASEB1 P3 ...
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Table 11-2 56F8357 -160 MAPBGA Package Identification by Pin Number (Continued) Ball Ball Signal Name No. No. J3 A15 L10 K2 D9 P10 E5 V N10 DD_IO K4 D10 P11 ...
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X D LASER MARK FOR PIN 1 Y IDENTIFICATION IN THIS AREA E 0. 13X 3 b 160X 0. VIEW M-M 0.10 Z Figure 11-3 160-pin MBGA Mechanical Information ...
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Package and Pin-Out Information This section contains package and pin-out information for the 56F8157. This device comes in a 160-pin Low-profile Quad Flat Pack (LQFP). package, Figure 11-5 shows the mechanical parameters for this package, and for the ...
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Table 11-3 56F8157 160-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name DD_IO CLKO 43 4 TXD0 44 5 RXD0 45 6 SCLK1 46 7 MOSI1 47 ...
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Table 11-3 56F8157 160-Pin LQFP Package Identification by Pin Number (Continued) Signal Pin No. Pin No. Name 26 A15 DD_IO 32 D10 72 ...
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156X C e/2 4X SEATING PLANE θ2 θ3 S DETAIL F Figure 11-5 160-pin LQFP Mechanical Information Freescale Semiconductor Preliminary 160X 0. 0.20 H A-B ...
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Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature θJΑ where Ambient temperature for the package ( ...
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The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small ...
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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V and V circuits. DD ...
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Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Supply Part Voltage MC56F8357 3.0–3.6 V Low-Profile Quad Flat ...
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Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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Freescale Semiconductor Preliminary 56F8357 Technical Data, Rev. 15 Power Distribution and I/O Ring Implementation 175 ...
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Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC56F8357 Rev. 15 ...