SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 931

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 41-14. Buffer Structure when classic ADC and touchscreen channels are interleaved
11053B–ATARM–22-Sep-11
trig.event1
trig.event2
trig.eventN
trig.event1
trig.event2
trig.event3
trig.eventN
trig.eventN+1
trig.event4
Assuming ADC_TSMR(TSMOD) = 1
ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0
ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) =1
Assuming ADC_TSMR(TSMOD) = 1
ADC_TSMR(TSAV) = 0 ADC_TSMR(TSFREQ) = 1
ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) = 1
DMA Buffer
Structure
DMA Buffer
Structure
8
0
1
8
0
1
8
0
1
0
1
8
0
1
8
8
8
8
0
1
8
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_CDR8
ADC_CDR8
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
Base Address (BA)
BA + 0x02
BA + 0x04
BA + 0x06
BA + 0x08
BA + 0x0A
BA + [(N-1) * 6]
BA + [(N-1) * 6]+ 0x02
BA + [(N-1) * 6]+ 0x04
BA + [(N-1) * 8]+ 0x06
DMA Transfer
Base Address (BA)
BA + 0x02
BA + 0x04
BA + 0x06
BA + 0x08
BA + 0x0A
BA + 0x0c
BA + 0x0e
BA + [(N-1) * 8]
BA + [(N-1) * 8]+ 0x02
BA + [(N-1) * 8]+ 0x04
DMA Transfer
trig.event1
trig.event2
trig.eventN
trig.event1
trig.event2
trig.event3
trig.event4
trig.eventN
trig.eventN+1
Assuming ADC_TSMR(TSMOD) = 1
ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) =
ADC_CHSR = 0x000_0100 , ADC_EMR(TAG)
Assuming ADC_TSMR(TSMOD) = 1
ADC_TSMR(TSAV) = 1 ADC_TSMR(TSFREQ
ADC_CHSR = 0x000_0100 , ADC_EMR(TAG)
DMA Buffer
Structure
DMA Buffer
Structure
0
0
0
0
0
0
0
0
0
8
8
0
1
8
8
0
1
8
8
0
1
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
ADC_CDR8
ADC_CDR8
ADC_XPOSR
ADC_YPOSR
SAM9G35
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