SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 573

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• WAKE_UP: Wake Up CPU Interrupt
0 = cleared by setting the WAKE_UP bit in UDPHS_CLRINT.
1 = set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from
the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in
UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation.
Note:
• ENDOFRSM: End Of Resume Interrupt
0 = cleared by setting the ENDOFRSM bit in UDPHS_CLRINT.
1 = set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a
UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN.
• UPSTR_RES: Upstream Resume Interrupt
0 = cleared by setting the UPSTR_RES bit in UDPHS_CLRINT.
1 = set by hardware when the UDPHS controller is sending a resume signal called “upstream resume”. This triggers a
UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN.
• EPT_x: Endpoint x Interrupt
0 = reset when the UDPHS_EPTSTAx interrupt source is cleared.
1 = set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled
by the EPT_x bit in UDPHS_IEN.
• DMA_x: DMA Channel x Interrupt
0 = reset when the UDPHS_DMASTATUSx interrupt source is cleared.
1 = set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the
DMA_x bit in UDPHS_IEN.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
this interrupt is generated even if the device controller clock is disabled.
SAM9G35
SAM9G35
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573