SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 671

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Figure 35-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Figure 35-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
35.7.3
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
SPCK cycle (for reference)
SPCK cycle (for reference)
(from master)
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
(from slave)
(CPOL = 0)
(CPOL = 1)
(to slave)
(to slave)
Master Mode Operations
SPCK
SPCK
MOSI
MISO
SPCK
SPCK
MOSI
MISO
NSS
NSS
* Not defined, but normally MSB of previous character received.
*
When configured in Master Mode, the SPI operates on the clock generated by the internal pro-
grammable baud rate generator. It fully controls the data transfers to and from the slave(s)
* Not defined but normally LSB of previous character transmitted.
MSB
1
1
MSB
MSB
MSB
2
2
6
6
6
6
3
3
5
5
5
5
4
4
4
4
4
4
5
5
3
3
3
3
6
6
6
2
2
2
2
7
7
1
1
1
1
8
8
LSB
LSB
LSB
SAM9G35
SAM9G35
LSB
*
671
671

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