SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 505

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.6
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Write Protection Registers
To prevent any single software error that may corrupt DMAC behavior, the DMAC address
space can be write-protected by setting the WPEN bit in the
ter”
If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the
DMAC Write Protect Status Register (MCI_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.
The WPVS flag is reset by writing the DMAC Write Protect Mode Register (DMAC_WPMR) with
the appropriate access key, WPKEY.
The protected registers are:
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“DMAC Global Configuration Register” on page 507
“DMAC Enable Register” on page 508
“DMAC Channel x [x = 0..7] Source Address Register” on page 518
“DMAC Channel x [x = 0..7] Destination Address Register” on page 519
“DMAC Channel x [x = 0..7] Descriptor Address Register” on page 520
“DMAC Channel x [x = 0..7] Control A Register” on page 521
“DMAC Channel x [x = 0..7] Control B Register” on page 523
“DMAC Channel x [x = 0..7] Configuration Register” on page 525
“DMAC Channel x [x = 0..7] Source Picture in Picture Configuration Register” on page 527
“DMAC Channel x [x = 0..7] Destination Picture in Picture Configuration Register” on page
528
(DMAC_WPMR).
“DMAC Write Protect Mode Regis-
SAM9G35
SAM9G35
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