SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 238

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

23.7.1
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• P0-P31: PIO Enable
0: No effect.
1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
23.7.2
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• P0-P31: PIO Disable
0: No effect.
1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
238
238
P31
P23
P15
P31
P23
P15
P7
P7
31
23
15
31
23
15
7
7
SAM9G35
SAM9G35
PIO Enable Register
PIO Disable Register
P30
P22
P14
P30
P22
P14
P6
P6
30
22
14
30
22
14
PIO_PER
0xFFFFF400 (PIOA), 0xFFFFF600 (PIOB), 0xFFFFF800 (PIOC), 0xFFFFFA00 (PIOD)
Write-only
6
PIO_PDR
0xFFFFF404 (PIOA), 0xFFFFF604 (PIOB), 0xFFFFF804 (PIOC), 0xFFFFFA04 (PIOD)
Write-only
6
P13
P13
P29
P21
P29
P21
P5
P5
29
21
13
29
21
13
5
5
P28
P20
P12
P28
P20
P12
P4
P4
28
20
12
28
20
12
4
4
“PIO Write Protect Mode Register”
“PIO Write Protect Mode Register”
P11
P11
P27
P19
P27
P19
P3
P3
27
19
11
27
19
11
3
3
P26
P18
P10
P26
P18
P10
P2
P2
26
18
10
26
18
10
2
2
.
.
P25
P17
P25
P17
P9
P1
P9
P1
25
17
25
17
9
1
9
1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
P24
P16
P24
P16
P8
P0
P8
P0
24
16
24
16
8
0
8
0