SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1234

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 46-23. In Full Speed
46.13 Analog-to-Digital Converter (ADC)
Table 46-24. Channel Conversion Time and ADC Clock
Note:
1234
1234
Symbol
t
t
t
Parameter
ADC Clock Frequency
Startup Time
Track and Hold Acquisition Time (TTH)
Conversion Time (TCT)
Throughput Rate
FR
FE
FRFM
1. The Track-and-Hold Acquisition Time is given by:
SAM9G35
SAM9G35
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conversion
time is given by:
The full speed is obtained for an input source impedance of < 50
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according to this
Track and Hold Acquisition Time, also called Sampled and Hold Time.
TTH (ns)
Parameter
Transition Rise Time
Transition Fall Time
Rise/Fall time Matching
TCT μs
=
=
Table 46-25. External Voltage Reference Input
Parameter
ADVREF Input Voltage Range
ADVREF Average Current
Current Consumption on VDDANA
500
---------- - MHz
Fclk
23
+
0.12
Z
Conditions
10-bit resolution mode
Return from Idle Mode
ADC Clock = 13.2 MHz
ADC Clock = 13.2 MHz
ADC Clock = 5 MHz
ADC Clock = 13.2 MHz
ADC Clock = 5 MHz
IN
Conditions
C
C
LOAD
LOAD
= 50 pF
= 50 pF
(1)
(1)
Conditions
(1)
(1)
(1)
maximum, or TTH = 500 ns.
Min
2.4
Min
0.5
Min
90
4
4
Typ
Typ
Typ
VDDANA
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Max
600
600
111.11
Max
13.2
1.74
440
192
Max
4.6
40
20
20
Units
Units
kSPS
MHz
Unit
μA
μA
V
μs
μs
μs
ns
ns
%