SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 757

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
38. Two-wire Interface (TWI)
38.1
38.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Description
Embedded Characteristics
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made
up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial
EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD
Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master
or a slave with sequential or single-byte access. Multiple master capability is supported. 20
Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the
bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of
core clock frequencies.
Below,
a full I2C compatible device.
Table 38-1.
Note:
Note:
I2C Standard
Standard Mode Speed (100 KHz)
Fast Mode Speed (400 KHz)
7 or 10 bits Slave Addressing
START BYTE
Repeated Start (Sr) Condition
ACK and NACK Management
Slope control and input filtering (Fast mode)
Clock stretching
Multi Master Capability
• 3 TWIs
• Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
• One, Two or Three Bytes for Slave Address
• Sequential Read-write Operations
• Master, Multi-master and Slave Mode Operation
• Bit Rate: Up to 400 Kbits
• General Call Supported in Slave mode
• SMBUS Quick Command Supported in Master Mode
• Connection to DMA Controller (DMAC) Channel Capabilities Optimizes Data Transfers in
Master Mode Only
Table 38-1
1. START + b000000001 + Ack + Sr
See
Table 38-1
(1)
Atmel TWI compatibility with i2C Standard
lists the compatibility level of the Atmel Two-wire Interface in Master Mode and
for details on compatibility with I²C Standard.
Atmel TWI
Supported
Supported
Supported
Not Supported
Supported
Supported
Not Supported
Supported
Supported
SAM9G35
SAM9G35
(Note:)
757
757

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