SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1007

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

44. Ethernet MAC 10/100 (EMAC)
44.1
44.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Description
Embedded Characteristics
The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 stan-
dard using an address checker, statistics and control registers, receive and transmit blocks, and
a DMA interface.
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis-
ter for matching multicast and unicast addresses. It can recognize the broadcast address of all
ones, copy all frames, and act on an external address match signal.
The statistics register block contains registers for counting various types of event associated
with transmit and receive operations. These registers, along with the status words stored in the
receive buffer list, enable software to generate network management statistics compatible with
IEEE 802.3.
• Supports RMII Interface to the Physical Layer
• Compatible with IEEE Standard 802.3
• 10 and 100 Mbit/s Operation
• Full- and Half-duplex Operation
• Statistics Counter Registers
• Interrupt Generation to Signal Receive and Transmit Completion
• DMA Master on Receive and Transmit Channels
• Transmit and Receive FIFOs
• Automatic Pad and CRC Generation on Transmitted Frames
• Automatic Discard of Frames Received with Errors
• Address Checking Logic Supports Up to Four Specific 48-bit Addresses
• Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory
• Hash Matching of Unicast and Multicast Destination Addresses
• Physical Layer Management through MDIO Interface
• Half-duplex Flow Control by Forcing Collisions on Incoming Frames
• Full-duplex Flow Control with Recognition of Incoming Pause Frames
•
• Multiple Buffers per Receive and Transmit Frame
• Jumbo Frames Up to 10240 bytes Supported
Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and
Frames
SAM9G35
SAM9G35
Priority Tagged
1007
1007