SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 585

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• ERR_OVFLW: Overflow Error Interrupt Enable
0 = no effect.
1 = enable Overflow Error Interrupt.
• RX_BK_RDY: Received OUT Data Interrupt Enable
0 = no effect.
1 = enable Received OUT Data Interrupt.
• TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
0 = no effect.
1 = enable Transmitted IN Data Complete Interrupt.
• TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable
0 = no effect.
1 = enable TX Packet Ready/Transaction Error Interrupt.
• RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable
0 = no effect.
1 = enable RX_SETUP/Error Flow ISO Interrupt.
• STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
0 = no effect.
1 = enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.
• NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable
0 = no effect.
1 = enable NAKIN/Bank Flush Error Interrupt.
• NAK_OUT: NAKOUT Interrupt Enable
0 = no effect.
1 = enable NAKOUT Interrupt.
• BUSY_BANK: Busy Bank Interrupt Enable
0 = no effect.
1 = enable Busy Bank Interrupt.
• SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
For OUT endpoints:
0 = no effect.
1 = enable Short Packet Interrupt.
For IN endpoints:
Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and
UDPHS_EPTCTLx register AUTOVALID bits are also set.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
SAM9G35
SAM9G35
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585