SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 859

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
39.7.10
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Write Protection Registers
Figure 39-57. Remote Loopback Mode Configuration
To prevent any single software error that may corrupt USART behavior, certain address spaces
can be write-protected by setting the WPEN bit in the USART Write Protect Mode Register
(US_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the USART Write
Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the USART Write Protect Mode Register (US_WPMR) with
the appropriate access key, WPKEY.
The protected registers are:
“USART Mode Register”
“USART Baud Rate Generator Register”
“USART Receiver Time-out Register”
“USART Transmitter Timeguard Register”
“USART FI DI RATIO Register”
“USART IrDA FILTER Register”
“USART Manchester Configuration Register”
Transmitter
Receiver
1
RXD
TXD
SAM9G35
SAM9G35
859
859

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