SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 477

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.4
31.4.1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Functional Description
Basic Definitions
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then
stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form
a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previ-
ously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMAC transfer and does not require
a handshaking interface to interact with the DMAC.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and
a destination peripheral on the same or different AMBA layer that occurs through the channel
FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to
the channel. If the destination peripheral is not memory, then a destination handshaking inter-
face is assigned to the channel. Source and destination handshaking interfaces can be assigned
dynamically by programming the channel registers.
Master interface: DMAC is a master on the AHB bus reading data from the source and writing it
to the destination over the AHB bus.
Slave interface: The APB interface over which the DMAC is programmed. The slave interface
in practice could be on the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake
between the DMAC and source or destination peripheral to control the transfer of a single or
chunk transfer between them. This interface is used to request, acknowledge, and control a
DMAC transaction. A channel can receive a request through one of two types of handshaking
interface: hardware or software.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or
chunk transfer between the DMAC and the source or destination peripheral.
Software handshaking interface: Uses software registers to control the transfer of a single or
chunk transfer between the DMAC and the source or destination peripheral. No special DMAC
handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing
an existing peripheral to the DMAC without modifying it.
Flow controller: The device (either the DMAC or source/destination peripheral) that determines
the length of and terminates a DMAC buffer transfer. If the length of a buffer is known before
enabling the channel, then the DMAC should be programmed as the flow controller. If the length
of a buffer is not known prior to enabling the channel, the source or destination peripheral needs
to terminate a buffer transfer. In this mode, the peripheral is the flow controller.
Transfer hierarchy:
buffer transfers, chunk or single, and AMBA transfers (single or burst) for non-memory peripher-
als.
Figure 31-3 on page 478
Figure 31-2 on page 478
shows the transfer hierarchy for memory.
illustrates the hierarchy between DMAC transfers,
SAM9G35
SAM9G35
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