SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 508

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.7.2
Name:
Address:
Access:
Reset:
This register can only be written if the WPEN bit is cleared in
• ENABLE
0: DMA Controller is disabled.
1: DMA Controller is enabled.
31.7.3
Name:
Address:
Access:
Reset:
• DSREQx
Request a destination single transfer on channel i.
• SSREQx
Request a source single transfer on channel i.
508
508
DSREQ7
DSREQ3
31
23
15
31
23
15
–
–
–
7
–
–
–
7
SAM9G35
SAM9G35
DMAC Enable Register
DMAC Software Single Request Register
0xFFFFEC04 (0), 0xFFFFEE04 (1)
Read-write
0x00000000
0xFFFFEC08 (0), 0xFFFFEE08 (1)
DMAC_EN
DMAC_SREQ
Read-write
0x00000000
SSREQ7
SSREQ3
30
22
14
30
22
14
–
–
–
6
–
–
–
6
DSREQ6
DSREQ2
29
21
13
29
21
13
–
–
–
5
–
–
–
5
SSREQ6
SSREQ2
28
20
12
28
20
12
–
–
–
4
–
–
–
4
“DMAC Write Protect Mode Register”
DSREQ5
DSREQ1
27
19
11
27
19
11
–
–
–
3
–
–
–
3
SSREQ5
SSREQ1
26
18
10
26
18
10
–
–
–
2
–
–
–
2
DSREQ4
DSREQ0
25
17
25
17
–
–
9
–
1
–
–
–
9
1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
SSREQ4
SSREQ0
ENABLE
24
16
24
16
–
–
8
–
0
–
–
8
0