SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 523

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.7.17
Name:
Address:
Access:
Reset:
This register can only be written if the WPEN bit is cleared in
• SIF: Source Interface Selection Field
• DIF: Destination Interface Selection Field
• SRC_PIP: Source Picture-in-Picture Mode
0 (DISABLE): Picture-in-Picture mode is disabled. The source data area is contiguous.
1 (ENABLE): Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the
address is automatically incremented by a user defined amount.
• DST_PIP: Destination Picture-in-Picture Mode
0 (DISABLE): Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 (ENABLE): Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary
the address is automatically incremented by a user-defined amount.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Value
00
01
Value
00
01
AUTO
31
23
15
–
7
–
DMAC Channel x [x = 0..7] Control B Register
DMAC_CTRLBx [x = 0..7]
0xFFFFEC4C (0)[0], 0xFFFFEC74 (0)[1], 0xFFFFEC9C (0)[2], 0xFFFFECC4 (0)[3], 0xFFFFECEC (0)[4],
0xFFFFED14 (0)[5], 0xFFFFED3C (0)[6], 0xFFFFED64 (0)[7], 0xFFFFEE4C (1)[0], 0xFFFFEE74 (1)[1],
0xFFFFEE9C (1)[2], 0xFFFFEEC4 (1)[3], 0xFFFFEEEC (1)[4], 0xFFFFEF14 (1)[5], 0xFFFFEF3C (1)[6],
0xFFFFEF64 (1)[7]
Read-write
0x00000000
IEN
FC
30
22
14
–
6
–
Name
AHB_IF0
AHB_IF1
Name
AHB_IF0
AHB_IF1
29
21
13
5
DST_INCR
Description
The source
The source
Description
The destination
The destination
DIF
DST_DSCR
DST_PIP
28
20
12
transfer is done via AHB-Lite Interface 0
transfer is done via AHB-Lite Interface 1
4
transfer is done via AHB-Lite Interface 0
transfer is done via AHB-Lite Interface 1
“DMAC Write Protect Mode Register”
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
25
17
–
9
–
1
.
SRC_INCR
SAM9G35
SAM9G35
SIF
SRC_DSCR
SRC_PIP
24
16
8
0
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