SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 924

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.7.7
924
SAM9G35
Sequence and Noise Filtering
Figure 41-9. Touchscreen Switches Implementation
The ADC Controller can manage ADC conversions and Touchscreen measurement. On each
trigger event the sequence of ADC conversions is performed as described in
”Sleep Mode and Conversion
fied in number of trigger events by writing the TSFREQ parameter in the “ADC Touchscreen
Mode Register”. An internal counter counts triggers up to TSFREQ, and every time it rolls out, a
Touchscreen sequence is appended to the classic ADC conversion sequence (see
10).
Additionally the user can average multiple Touchscreen measures by writing the TSAV parame-
ter in the “ADC Touchscreen Mode Register”. This can be 1, 2, 4 or 8 measures performed on
consecutive triggers as illustrated in
ter must be greater or equal to the TSAV parameter.
L
U
L
L
VDDANA for Xpos
SENSE
GND for Ypos
L
VDDANA
U
U
R
L
R
L
L
Sequencer”. The Touchscreen measure frequency can be speci-
Figure 41-10
VDDANA
VDDANA
VDDANA
GND
GND
GND
bellow. Consequently, the TSFREQ parame-
0
1
2
3
4
To the ADC
U
L
R
R
Sense
VDDANA for Ypos
GND for Xpos
GND
11053B–ATARM–22-Sep-11
Section 41.6.6
Figure 41-