ATTINY20-XU Atmel, ATTINY20-XU Datasheet - Page 57

• Manufacturer Part Number: ATTINY20-XU
• Description: MCU AVR 2KB FLASH 12MHZ 14TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-XU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8235B–AVR–04/11
Table 10-8 on page 57
overriding signals shown in
Table 10-8.
1.
2.
Table 10-9.
1.
Note:
Signal
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
RSTDISBL is 1 when the configuration bit is “0” (programmed)
CKOUT is 1 when the configuration bit is “0” (programmed)
EXT_CLOCK = external clock is selected as system clock.
When TWI is enabled the slew rate control and spike filter are activate on PB1. This is not illus-
trated in
TWEN • SPE • MSTR • SPI_MASTER_OUT +
RSTDISBL
RSTDISBL
TWEN + (SPE • MSTR) + OC1A_ENABLE
Overriding Signals for Alternate Functions in PB[3:2]
Overriding Signals for Alternate Functions in PB[1:0]
Figure 10-6 on page
PB3/
TWEN • (SPE + MSTR) • OC1A
PB1/OC1A/SDA/MOSI/PCINT9
PCINT11 Input
PCINT9 / SPI Slave Input
RESET/
RSTDISBL
(SPE • MSTR) + TWEN
RSTDISBL
RSTDISBL
(1)
(1)
and
TWEN • SDA_OUT
+ (PCINT11 • PCIE1)
PCINT9 • PCIE1
PCINT9 • PCIE1
• PCINT11 • PCIE1
1
0
0
0
Figure 10-6 on page
Table 10-9 on page 57
SDA Input
PCINT11
(1)
(1)
(1)
0
0
0
50. The spike filter is connected between AIOxn and the TWI.
CKOUT
OC1B_ENABLE • OC1B + CKOUT • (SPE + MSTR)
50.
PB2/INT0/OC0A/OC1B/MISO/CKOUT/PCINT10
CKOUT + OC0A_ENABLE + OC1B_ENABLE +
SPI_SLAVE_OUT + CKOUT • (SPE + MSTR) •
relate the alternate functions of Port B to the
(2)
INT0 / PCINT10 / SPI Master Input
• System Clock + CKOUT • SPE • MSTR •
(PCINT10 • PCIE1) + INT0
CKOUT
(PCINT10 • PCIE1) + INT0
• OC1B_ENABLE • OC0A
EXT_CLOCK
( EXT_CLOCK
(EXT_CLOCK
CLOCK / PCINT8 / T0 Input
(SPE • MSTR)
PB0/T0/CLKI/PCINT8
(2)
CKOUT
CKOUT
+ (SPE • MSTR)
EXT_CLOCK
EXT_CLOCK
EXT_CLOCK
0
0
(1)
(1)
(1)
(2)
(2)
+ (PCINT8 • PCIE1)
• PCINT8 • PCIE1)
0
0
0
0
• PWR_DOWN ) +
ATtiny20
(1)
(1)
(1)
57