ATTINY20-XU Atmel, ATTINY20-XU Datasheet - Page 54

• Manufacturer Part Number: ATTINY20-XU
• Description: MCU AVR 2KB FLASH 12MHZ 14TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-XU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

54
ATtiny20
Table 10-4
shown in
Table 10-4.
Note:
Table 10-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
When TWI is enabled the slew rate control and spike filter are activated on PA7. This is not illus-
trated in
module.
Figure 10-6 on page
SCK_OUT + (SPE + MSTR) •
(PCINT4 • PCIE0) + ADC4D
and
PCINT7 • PCIE0 + ADC7D
TWEN + (SPE • MSTR) +
PA7/ADC7/OC0B/ICP1/
TWEN • (SPE • MSTR •
TWEN + (SPE • MSTR)
ICP1 / SCK / T1 / SCL /
Overriding Signals for Alternate Functions in PA[7:5]
Overriding Signals for Alternate Functions in PA[4:2]
T1/SCL/SCK/PCINT7
PA4/ADC4/PCINT4
TWEN • SCL_OUT
Figure 10-6 on page
(PCINT4 • PCIE0)
ADC7 / SCL Input
Table 10-5
PCINT7 • PCIE0
OC0B_ENABLE
PCINT4 input
PCINT7 Input
ADC4 Input
OC0B)
0
0
0
0
0
0
0
0
0
0
relate the alternate functions of Port A to the overriding signals
50.
50. The spike filter is connected between AIOxn and the TWI
(PCINT3 • PCIE0) + ADC3D
PCINT6 • PCIE0 + ADC6D
PA6/ADC6/SS/PCINT6
SPI SS / PCINT6 Input
PA3/ADC3/PCINT3
PCINT6 • PCIE0
PCINT3 • PCIE0
PCINT1 Input
SPE • MSTR
ADC6 Input
ADC3 Input
0
0
0
0
0
0
0
0
0
0
0
0
0
PCINT5 • PCIE0 + ADC5D
(PCINT2 • PCIE0) + ADC2D
ADC2 / Analog Comparator
PA2/ADC2/AIN1/PCINT2
PA5/ADC5/PCINT5
PCINT5 • PCIE0
PCINT3 • PCIE0
PCINT5 Input
Negative Input
PCINT0 Input
ADC5 Input
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8235B–AVR–04/11