ATTINY20-XU Atmel, ATTINY20-XU Datasheet - Page 155

• Manufacturer Part Number: ATTINY20-XU
• Description: MCU AVR 2KB FLASH 12MHZ 14TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-XU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.3.7
18.3.8
18.3.9
8235B–AVR–04/11
Serial Data Reception
Serial Data Transmission
Collision Detection Exception
Figure 18-5. Data changing and Data sampling.
The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the
layer is in Receive mode, waiting for a start bit. The mode of operation is controlled by the
access layer.
When the TPI physical layer is in receive mode, data reception is started as soon as a start bit
has been detected. Each bit that follows the start bit will be sampled at the rising edge of the
TPICLK and shifted into the shift register until the second stop bit has been received. When the
complete frame is present in the shift register the received data will be available for the TPI
access layer.
There are three possible exceptions in the receive mode: frame error, parity error and break
detection. All these exceptions are signalized to the TPI access layer, which then enters the
error state and puts the TPI physical layer into receive mode, waiting for a BREAK character.
When the TPI physical layer is ready to send a new frame it initiates data transmission by load-
ing the shift register with the data to be transmitted. When the shift register has been loaded with
new data, the transmitter shifts one complete frame out on the TPIDATA line at the transfer rate
given by TPICLK.
If a collision is detected during transmission, the output driver is disabled. The TPI access layer
enters the error state and the TPI physical layer is put into receive mode, waiting for a BREAK
character.
The TPI physical layer uses one bi-directional data line for both data reception and transmission.
A possible drive contention may occur, if the external programmer and the TPI physical layer
drive the TPIDATA line simultaneously. In order to reduce the effect of the drive contention, a
collision detection mechanism is supported. The collision detection is based on the way the TPI
physical layer drives the TPIDATA line.
• Frame Error Exception. The frame error exception indicates the state of the stop bit. The
• Parity Error Exception. The parity of the data bits is calculated during the frame reception.
• Break Detection Exception. The Break detection exception is given when a complete frame of
frame error exception is set if the stop bit was read as zero.
After the frame is received completely, the result is compared with the parity bit of the frame.
If the comparison fails the parity error exception is signalized.
all zeros has been received.
TPICLK
TPIDATA
SAMPLE
SETUP
ATtiny20
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