ATTINY20-XU Atmel, ATTINY20-XU Datasheet - Page 158

• Manufacturer Part Number: ATTINY20-XU
• Description: MCU AVR 2KB FLASH 12MHZ 14TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-XU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.1
18.5.2
158
ATtiny20
SLD - Serial LoaD from data space using indirect addressing
SST - Serial STore to data space using indirect addressing
The TPI instruction set is summarised in
Table 18-1.
The SLD instruction uses indirect addressing to load data from the data space to the TPI physi-
cal layer shift-register for serial read-out. The data space location is pointed by the Pointer
Register (PR), where the address must have been stored before data is accessed. The Pointer
Register can either be left unchanged by the operation, or it can be post-incremented, as shown
in
Table 18-2.
The SST instruction uses indirect addressing to store into data space the byte that is shifted into
the physical layer shift register. The data space location is pointed by the Pointer Register (PR),
where the address must have been stored before the operation. The Pointer Register can be
either left unchanged by the operation, or it can be post-incremented, as shown in
Table 18-3.
Mnemonic
SLD
SLD
SST
SST
SSTPR
SIN
SOUT
SLDCS
SSTCS
SKEY
Operation
data
data
Operation
DS[PR]
DS[PR]
Table
←
←
18-2.
←
←
DS[PR]
DS[PR]
data
data
Instruction Set Summary
The Serial Load from Data Space (SLD) Instruction
The Serial Store to Data Space (SLD) Instruction
Operand
data, PR
data, PR+
PR, data
PR+, data
PR, a
data, a
a, data
data, a
a, data
Key, {8{data}}
Opcode
0010 0000
0010 0100
Opcode
0110 0000
0110 0100
Serial IN from data space
Serial KEY
Description
Serial LoaD from data space using indirect
addressing
Serial LoaD from data space using indirect
addressing and post-increment
Serial STore to data space using indirect
addressing
Serial STore to data space using indirect
addressing and post-increment
Serial STore to Pointer Register using direct
addressing
Serial OUT to data space
Serial LoaD from Control and Status space
using direct addressing
Serial STore to Control and Status space
using direct addressing
Table
18-1.
Remarks
PR
PR
Remarks
PR
PR
←
←
←
←
PR
PR + 1
PR
PR + 1
Register
Unchanged
Post increment
Register
Unchanged
Post increment
Operation
data
data
PR
DS[PR]
DS[PR]
PR
PR[a]
data
I/O[a]
data
CSS[a]
Key
←
←
←
←
←
←
←
←
8235B–AVR–04/11
←
Table
PR+1
PR+1
←
{8{data}}
←
←
DS[PR]
DS[PR]
I/O[a]
CSS[a]
data
data
data
data
data
18-3.